xref: /kvm-unit-tests/riscv/cstart.S (revision 6fba6b84bae33db2b7fda1d4ff50f1d78e83adba) 
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Boot entry point and assembler functions for riscv.
4 *
5 * Copyright (C) 2023, Ventana Micro Systems Inc., Andrew Jones <ajones@ventanamicro.com>
6 */
7#include <asm/asm-offsets.h>
8#include <asm/csr.h>
9
10#if __riscv_xlen == 64
11#define __REG_SEL(a, b) a
12#elif __riscv_xlen == 32
13#define __REG_SEL(a, b) b
14#else
15#error "Unexpected __riscv_xlen"
16#endif
17
18#define REG_L	__REG_SEL(ld, lw)
19#define REG_S	__REG_SEL(sd, sw)
20#define SZREG	__REG_SEL(8, 4)
21
22#define FP_SIZE 16
23
24.macro push_fp, ra=ra
25	addi	sp, sp, -FP_SIZE
26	REG_S	\ra, (FP_SIZE - SZREG)(sp)
27	REG_S	fp, (FP_SIZE - 2*SZREG)(sp)
28	addi	fp, sp, FP_SIZE
29.endm
30
31.macro pop_fp
32	REG_L	ra, (FP_SIZE - SZREG)(sp)
33	REG_L	fp, (FP_SIZE - 2*SZREG)(sp)
34	addi	sp, sp, FP_SIZE
35.endm
36
37.macro zero_range, tmp1, tmp2
389998:	beq	\tmp1, \tmp2, 9997f
39	REG_S	zero, 0(\tmp1)
40	addi	\tmp1, \tmp1, 8
41	j	9998b
429997:
43.endm
44
45	.section .init
46
47/*
48 * The hartid of the current core is in a0
49 * The address of the devicetree is in a1
50 *
51 * See Linux kernel doc Documentation/riscv/boot.rst
52 */
53.global start
54start:
55	/*
56	 * Stash the hartid in scratch and shift the dtb address into a0.
57	 * thread_info_init() will later promote scratch to point at thread
58	 * local storage.
59	 */
60	csrw	CSR_SSCRATCH, a0
61	mv	a0, a1
62
63	/*
64	 * Update all R_RISCV_RELATIVE relocations using the table
65	 * of Elf32_Rela/Elf64_Rela entries between reloc_start/end.
66	 * The build will not emit other relocation types.
67	 */
68	la	a1, reloc_start
69	la	a2, reloc_end
70	la	a3, start			// base
711:
72	bge	a1, a2, 1f
73	REG_L	a4, ELF_RELA_OFFSET(a1)		// r_offset
74	REG_L	a5, ELF_RELA_ADDEND(a1)		// r_addend
75	add	a4, a3, a4			// addr = base + r_offset
76	add	a5, a3, a5			// val = base + r_addend
77	REG_S	a5, 0(a4)			// *addr = val
78	addi	a1, a1, ELF_RELA_SIZE
79	j	1b
80
811:
82	/* zero BSS */
83	la	a1, bss
84	la	a2, ebss
85	zero_range a1, a2
86
87	/* zero and set up stack */
88	la	sp, stacktop
89	li	a1, -8192
90	add	a1, sp, a1
91	zero_range a1, sp
92	mv	fp, zero			// Ensure fp starts out as zero
93
94	/* set up exception handling */
95	la	a1, exception_vectors
96	csrw	CSR_STVEC, a1
97
98	/* complete setup */
99	la	a1, stacktop			// a1 is the base of free memory
100	mv	a2, zero			// clear a2 for xlen=32
101	call	setup				// a0 is the addr of the dtb
102
103	/* run the test */
104	la	a0, __argc
105	REG_L	a0, 0(a0)
106	la	a1, __argv
107	la	a2, __environ
108	call	main
109	call	exit
110	j	halt
111
112	.text
113
114.balign 4
115.global halt
116halt:
1171:	wfi
118	j	1b
119
120/*
121 * Save context to address in a0.
122 * For a0, sets PT_A0(a0) to the contents of PT_ORIG_A0(a0).
123 * Clobbers a1.
124 */
125.macro save_context
126	REG_S	ra, PT_RA(a0)			// x1
127	REG_S	sp, PT_SP(a0)			// x2
128	REG_S	gp, PT_GP(a0)			// x3
129	REG_S	tp, PT_TP(a0)			// x4
130	REG_S	t0, PT_T0(a0)			// x5
131	REG_S	t1, PT_T1(a0)			// x6
132	REG_S	t2, PT_T2(a0)			// x7
133	REG_S	s0, PT_S0(a0)			// x8 / fp
134	REG_S	s1, PT_S1(a0)			// x9
135	/* a0 */				// x10
136	REG_S   a1, PT_A1(a0)			// x11
137	REG_S	a2, PT_A2(a0)			// x12
138	REG_S	a3, PT_A3(a0)			// x13
139	REG_S	a4, PT_A4(a0)			// x14
140	REG_S	a5, PT_A5(a0)			// x15
141	REG_S	a6, PT_A6(a0)			// x16
142	REG_S	a7, PT_A7(a0)			// x17
143	REG_S	s2, PT_S2(a0)			// x18
144	REG_S	s3, PT_S3(a0)			// x19
145	REG_S	s4, PT_S4(a0)			// x20
146	REG_S	s5, PT_S5(a0)			// x21
147	REG_S	s6, PT_S6(a0)			// x22
148	REG_S	s7, PT_S7(a0)			// x23
149	REG_S	s8, PT_S8(a0)			// x24
150	REG_S	s9, PT_S9(a0)			// x25
151	REG_S	s10, PT_S10(a0)			// x26
152	REG_S	s11, PT_S11(a0)			// x27
153	REG_S	t3, PT_T3(a0)			// x28
154	REG_S	t4, PT_T4(a0)			// x29
155	REG_S	t5, PT_T5(a0)			// x30
156	REG_S	t6, PT_T6(a0)			// x31
157	csrr	a1, CSR_SEPC
158	REG_S	a1, PT_EPC(a0)
159	csrr	a1, CSR_SSTATUS
160	REG_S	a1, PT_STATUS(a0)
161	csrr	a1, CSR_STVAL
162	REG_S	a1, PT_BADADDR(a0)
163	csrr	a1, CSR_SCAUSE
164	REG_S	a1, PT_CAUSE(a0)
165	REG_L	a1, PT_ORIG_A0(a0)
166	REG_S	a1, PT_A0(a0)
167.endm
168
169/*
170 * Restore context from address in a0.
171 * Also restores a0.
172 */
173.macro restore_context
174	REG_L	ra, PT_RA(a0)			// x1
175	REG_L	sp, PT_SP(a0)			// x2
176	REG_L	gp, PT_GP(a0)			// x3
177	REG_L	tp, PT_TP(a0)			// x4
178	REG_L	t0, PT_T0(a0)			// x5
179	REG_L	t1, PT_T1(a0)			// x6
180	REG_L	t2, PT_T2(a0)			// x7
181	REG_L	s0, PT_S0(a0)			// x8 / fp
182	REG_L	s1, PT_S1(a0)			// x9
183	/* a0 */				// x10
184	/* a1 */				// x11
185	REG_L	a2, PT_A2(a0)			// x12
186	REG_L	a3, PT_A3(a0)			// x13
187	REG_L	a4, PT_A4(a0)			// x14
188	REG_L	a5, PT_A5(a0)			// x15
189	REG_L	a6, PT_A6(a0)			// x16
190	REG_L	a7, PT_A7(a0)			// x17
191	REG_L	s2, PT_S2(a0)			// x18
192	REG_L	s3, PT_S3(a0)			// x19
193	REG_L	s4, PT_S4(a0)			// x20
194	REG_L	s5, PT_S5(a0)			// x21
195	REG_L	s6, PT_S6(a0)			// x22
196	REG_L	s7, PT_S7(a0)			// x23
197	REG_L	s8, PT_S8(a0)			// x24
198	REG_L	s9, PT_S9(a0)			// x25
199	REG_L	s10, PT_S10(a0)			// x26
200	REG_L	s11, PT_S11(a0)			// x27
201	REG_L	t3, PT_T3(a0)			// x28
202	REG_L	t4, PT_T4(a0)			// x29
203	REG_L	t5, PT_T5(a0)			// x30
204	REG_L	t6, PT_T6(a0)			// x31
205	REG_L	a1, PT_EPC(a0)
206	csrw	CSR_SEPC, a1
207	REG_L	a1, PT_STATUS(a0)
208	csrw	CSR_SSTATUS, a1
209	REG_L	a1, PT_BADADDR(a0)
210	csrw	CSR_STVAL, a1
211	REG_L	a1, PT_CAUSE(a0)
212	csrw	CSR_SCAUSE, a1
213	REG_L	a1, PT_A1(a0)
214	REG_L	a0, PT_A0(a0)
215.endm
216
217.balign 4
218.global exception_vectors
219exception_vectors:
220	REG_S	a0, (-PT_SIZE - FP_SIZE + PT_ORIG_A0)(sp)
221	addi	a0, sp, -PT_SIZE - FP_SIZE
222	save_context
223	/*
224	 * Set a frame pointer "ra" which points to the last instruction.
225	 * Add 1 to it, because pretty_print_stacks.py subtracts 1.
226	 */
227	REG_L	a1, PT_EPC(a0)
228	addi	a1, a1, 1
229	push_fp	a1
230	mv	sp, a0
231	call	do_handle_exception
232	mv	a0, sp
233	restore_context
234	sret
235