1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Boot entry point and assembler functions for riscv. 4 * 5 * Copyright (C) 2023, Ventana Micro Systems Inc., Andrew Jones <ajones@ventanamicro.com> 6 */ 7#include <asm/asm-offsets.h> 8#include <asm/csr.h> 9 10#if __riscv_xlen == 64 11#define __REG_SEL(a, b) a 12#elif __riscv_xlen == 32 13#define __REG_SEL(a, b) b 14#else 15#error "Unexpected __riscv_xlen" 16#endif 17 18#define REG_L __REG_SEL(ld, lw) 19#define REG_S __REG_SEL(sd, sw) 20 21.macro zero_range, tmp1, tmp2 229998: beq \tmp1, \tmp2, 9997f 23 REG_S zero, 0(\tmp1) 24 addi \tmp1, \tmp1, 8 25 j 9998b 269997: 27.endm 28 29 .section .init 30 31/* 32 * The hartid of the current core is in a0 33 * The address of the devicetree is in a1 34 * 35 * See Linux kernel doc Documentation/riscv/boot.rst 36 */ 37.global start 38start: 39 /* 40 * Stash the hartid in scratch and shift the dtb 41 * address into a0 42 */ 43 csrw CSR_SSCRATCH, a0 44 mv a0, a1 45 46 /* 47 * Update all R_RISCV_RELATIVE relocations using the table 48 * of Elf32_Rela/Elf64_Rela entries between reloc_start/end. 49 * The build will not emit other relocation types. 50 */ 51 la a1, reloc_start 52 la a2, reloc_end 53 la a3, start // base 541: 55 bge a1, a2, 1f 56 REG_L a4, ELF_RELA_OFFSET(a1) // r_offset 57 REG_L a5, ELF_RELA_ADDEND(a1) // r_addend 58 add a4, a3, a4 // addr = base + r_offset 59 add a5, a3, a5 // val = base + r_addend 60 REG_S a5, 0(a4) // *addr = val 61 addi a1, a1, ELF_RELA_SIZE 62 j 1b 63 641: 65 /* zero BSS */ 66 la a1, bss 67 la a2, ebss 68 zero_range a1, a2 69 70 /* zero and set up stack */ 71 la sp, stacktop 72 li a1, -8192 73 add a1, sp, a1 74 zero_range a1, sp 75 76 /* set up exception handling */ 77 //TODO 78 79 /* complete setup */ 80 la a1, stacktop // a1 is the base of free memory 81 mv a2, zero // clear a2 for xlen=32 82 call setup // a0 is the addr of the dtb 83 84 /* run the test */ 85 la a0, __argc 86 REG_L a0, 0(a0) 87 la a1, __argv 88 la a2, __environ 89 call main 90 call exit 91 j halt 92 93 .text 94 95.balign 4 96.global halt 97halt: 981: wfi 99 j 1b 100