116c0b05fSPeter Xu /*
216c0b05fSPeter Xu * Intel IOMMU header
316c0b05fSPeter Xu *
416c0b05fSPeter Xu * Copyright (C) 2016 Red Hat, Inc.
516c0b05fSPeter Xu *
616c0b05fSPeter Xu * Authors:
716c0b05fSPeter Xu * Peter Xu <peterx@redhat.com>,
816c0b05fSPeter Xu *
916c0b05fSPeter Xu * This work is licensed under the terms of the GNU LGPL, version 2 or
1016c0b05fSPeter Xu * later.
1116c0b05fSPeter Xu *
1216c0b05fSPeter Xu * (From include/linux/intel-iommu.h)
1316c0b05fSPeter Xu */
1416c0b05fSPeter Xu
15*c865f654SCornelia Huck #ifndef _X86_INTEL_IOMMU_H_
16*c865f654SCornelia Huck #define _X86_INTEL_IOMMU_H_
1716c0b05fSPeter Xu
1816c0b05fSPeter Xu #include "libcflat.h"
1916c0b05fSPeter Xu #include "isr.h"
2016c0b05fSPeter Xu #include "smp.h"
2116c0b05fSPeter Xu #include "desc.h"
2292d2c192SPeter Xu #include "pci.h"
2316c0b05fSPeter Xu #include "asm/io.h"
243223ade2SPeter Xu #include "apic.h"
2516c0b05fSPeter Xu
2616c0b05fSPeter Xu #define Q35_HOST_BRIDGE_IOMMU_ADDR 0xfed90000ULL
2792d2c192SPeter Xu #define VTD_PAGE_SHIFT PAGE_SHIFT
2892d2c192SPeter Xu #define VTD_PAGE_SIZE PAGE_SIZE
2916c0b05fSPeter Xu
3016c0b05fSPeter Xu /*
3116c0b05fSPeter Xu * Intel IOMMU register specification
3216c0b05fSPeter Xu */
3316c0b05fSPeter Xu #define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */
3416c0b05fSPeter Xu #define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */
3516c0b05fSPeter Xu #define DMAR_CAP_REG_HI 0xc /* High 32-bit of DMAR_CAP_REG */
3616c0b05fSPeter Xu #define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */
3716c0b05fSPeter Xu #define DMAR_ECAP_REG_HI 0X14
3816c0b05fSPeter Xu #define DMAR_GCMD_REG 0x18 /* Global command */
3916c0b05fSPeter Xu #define DMAR_GSTS_REG 0x1c /* Global status */
4016c0b05fSPeter Xu #define DMAR_RTADDR_REG 0x20 /* Root entry table */
4116c0b05fSPeter Xu #define DMAR_RTADDR_REG_HI 0X24
4216c0b05fSPeter Xu #define DMAR_CCMD_REG 0x28 /* Context command */
4316c0b05fSPeter Xu #define DMAR_CCMD_REG_HI 0x2c
4416c0b05fSPeter Xu #define DMAR_FSTS_REG 0x34 /* Fault status */
4516c0b05fSPeter Xu #define DMAR_FECTL_REG 0x38 /* Fault control */
4616c0b05fSPeter Xu #define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data */
4716c0b05fSPeter Xu #define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr */
4816c0b05fSPeter Xu #define DMAR_FEUADDR_REG 0x44 /* Upper address */
4916c0b05fSPeter Xu #define DMAR_AFLOG_REG 0x58 /* Advanced fault control */
5016c0b05fSPeter Xu #define DMAR_AFLOG_REG_HI 0X5c
5116c0b05fSPeter Xu #define DMAR_PMEN_REG 0x64 /* Enable protected memory region */
5216c0b05fSPeter Xu #define DMAR_PLMBASE_REG 0x68 /* PMRR low addr */
5316c0b05fSPeter Xu #define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */
5416c0b05fSPeter Xu #define DMAR_PHMBASE_REG 0x70 /* PMRR high base addr */
5516c0b05fSPeter Xu #define DMAR_PHMBASE_REG_HI 0X74
5616c0b05fSPeter Xu #define DMAR_PHMLIMIT_REG 0x78 /* PMRR high limit */
5716c0b05fSPeter Xu #define DMAR_PHMLIMIT_REG_HI 0x7c
5816c0b05fSPeter Xu #define DMAR_IQH_REG 0x80 /* Invalidation queue head */
5916c0b05fSPeter Xu #define DMAR_IQH_REG_HI 0X84
6016c0b05fSPeter Xu #define DMAR_IQT_REG 0x88 /* Invalidation queue tail */
6116c0b05fSPeter Xu #define DMAR_IQT_REG_HI 0X8c
6216c0b05fSPeter Xu #define DMAR_IQA_REG 0x90 /* Invalidation queue addr */
6316c0b05fSPeter Xu #define DMAR_IQA_REG_HI 0x94
6416c0b05fSPeter Xu #define DMAR_ICS_REG 0x9c /* Invalidation complete status */
6516c0b05fSPeter Xu #define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr */
6616c0b05fSPeter Xu #define DMAR_IRTA_REG_HI 0xbc
6716c0b05fSPeter Xu #define DMAR_IECTL_REG 0xa0 /* Invalidation event control */
6816c0b05fSPeter Xu #define DMAR_IEDATA_REG 0xa4 /* Invalidation event data */
6916c0b05fSPeter Xu #define DMAR_IEADDR_REG 0xa8 /* Invalidation event address */
7016c0b05fSPeter Xu #define DMAR_IEUADDR_REG 0xac /* Invalidation event address */
7116c0b05fSPeter Xu #define DMAR_PQH_REG 0xc0 /* Page request queue head */
7216c0b05fSPeter Xu #define DMAR_PQH_REG_HI 0xc4
7316c0b05fSPeter Xu #define DMAR_PQT_REG 0xc8 /* Page request queue tail*/
7416c0b05fSPeter Xu #define DMAR_PQT_REG_HI 0xcc
7516c0b05fSPeter Xu #define DMAR_PQA_REG 0xd0 /* Page request queue address */
7616c0b05fSPeter Xu #define DMAR_PQA_REG_HI 0xd4
7716c0b05fSPeter Xu #define DMAR_PRS_REG 0xdc /* Page request status */
7816c0b05fSPeter Xu #define DMAR_PECTL_REG 0xe0 /* Page request event control */
7916c0b05fSPeter Xu #define DMAR_PEDATA_REG 0xe4 /* Page request event data */
8016c0b05fSPeter Xu #define DMAR_PEADDR_REG 0xe8 /* Page request event address */
8116c0b05fSPeter Xu #define DMAR_PEUADDR_REG 0xec /* Page event upper address */
8216c0b05fSPeter Xu #define DMAR_MTRRCAP_REG 0x100 /* MTRR capability */
8316c0b05fSPeter Xu #define DMAR_MTRRCAP_REG_HI 0x104
8416c0b05fSPeter Xu #define DMAR_MTRRDEF_REG 0x108 /* MTRR default type */
8516c0b05fSPeter Xu #define DMAR_MTRRDEF_REG_HI 0x10c
8616c0b05fSPeter Xu
8716c0b05fSPeter Xu #define VTD_GCMD_IR_TABLE 0x1000000
8816c0b05fSPeter Xu #define VTD_GCMD_IR 0x2000000
8916c0b05fSPeter Xu #define VTD_GCMD_QI 0x4000000
9016c0b05fSPeter Xu #define VTD_GCMD_WBF 0x8000000 /* Write Buffer Flush */
9116c0b05fSPeter Xu #define VTD_GCMD_SFL 0x20000000 /* Set Fault Log */
9216c0b05fSPeter Xu #define VTD_GCMD_ROOT 0x40000000
9316c0b05fSPeter Xu #define VTD_GCMD_DMAR 0x80000000
9416c0b05fSPeter Xu #define VTD_GCMD_ONE_SHOT_BITS (VTD_GCMD_IR_TABLE | VTD_GCMD_WBF | \
9516c0b05fSPeter Xu VTD_GCMD_SFL | VTD_GCMD_ROOT)
9616c0b05fSPeter Xu
9716c0b05fSPeter Xu /* Supported Adjusted Guest Address Widths */
9816c0b05fSPeter Xu #define VTD_CAP_SAGAW_SHIFT 8
9916c0b05fSPeter Xu /* 39-bit AGAW, 3-level page-table */
10016c0b05fSPeter Xu #define VTD_CAP_SAGAW_39bit (0x2ULL << VTD_CAP_SAGAW_SHIFT)
10116c0b05fSPeter Xu /* 48-bit AGAW, 4-level page-table */
10216c0b05fSPeter Xu #define VTD_CAP_SAGAW_48bit (0x4ULL << VTD_CAP_SAGAW_SHIFT)
10316c0b05fSPeter Xu #define VTD_CAP_SAGAW VTD_CAP_SAGAW_39bit
10416c0b05fSPeter Xu
10516c0b05fSPeter Xu /* Both 1G/2M huge pages */
10616c0b05fSPeter Xu #define VTD_CAP_SLLPS ((1ULL << 34) | (1ULL << 35))
10716c0b05fSPeter Xu
10816c0b05fSPeter Xu #define VTD_CONTEXT_TT_MULTI_LEVEL 0
10916c0b05fSPeter Xu #define VTD_CONTEXT_TT_DEV_IOTLB 1
11016c0b05fSPeter Xu #define VTD_CONTEXT_TT_PASS_THROUGH 2
11116c0b05fSPeter Xu
11216c0b05fSPeter Xu #define VTD_PTE_R (1 << 0)
11316c0b05fSPeter Xu #define VTD_PTE_W (1 << 1)
11416c0b05fSPeter Xu #define VTD_PTE_RW (VTD_PTE_R | VTD_PTE_W)
11516c0b05fSPeter Xu #define VTD_PTE_ADDR GENMASK_ULL(63, 12)
11616c0b05fSPeter Xu #define VTD_PTE_HUGE (1 << 7)
11716c0b05fSPeter Xu
11816c0b05fSPeter Xu extern void *vtd_reg_base;
11916c0b05fSPeter Xu #define vtd_reg(reg) ({ assert(vtd_reg_base); \
12016c0b05fSPeter Xu (volatile void *)(vtd_reg_base + reg); })
12116c0b05fSPeter Xu
vtd_writel(unsigned int reg,uint32_t value)12216c0b05fSPeter Xu static inline void vtd_writel(unsigned int reg, uint32_t value)
12316c0b05fSPeter Xu {
12416c0b05fSPeter Xu __raw_writel(value, vtd_reg(reg));
12516c0b05fSPeter Xu }
12616c0b05fSPeter Xu
vtd_writeq(unsigned int reg,uint64_t value)12716c0b05fSPeter Xu static inline void vtd_writeq(unsigned int reg, uint64_t value)
12816c0b05fSPeter Xu {
12916c0b05fSPeter Xu __raw_writeq(value, vtd_reg(reg));
13016c0b05fSPeter Xu }
13116c0b05fSPeter Xu
vtd_readl(unsigned int reg)13216c0b05fSPeter Xu static inline uint32_t vtd_readl(unsigned int reg)
13316c0b05fSPeter Xu {
13416c0b05fSPeter Xu return __raw_readl(vtd_reg(reg));
13516c0b05fSPeter Xu }
13616c0b05fSPeter Xu
vtd_readq(unsigned int reg)13716c0b05fSPeter Xu static inline uint64_t vtd_readq(unsigned int reg)
13816c0b05fSPeter Xu {
13916c0b05fSPeter Xu return __raw_readq(vtd_reg(reg));
14016c0b05fSPeter Xu }
14116c0b05fSPeter Xu
14216c0b05fSPeter Xu void vtd_init(void);
14392d2c192SPeter Xu void vtd_map_range(uint16_t sid, phys_addr_t iova, phys_addr_t pa, size_t size);
1447f2477c2SPeter Xu bool vtd_setup_msi(struct pci_dev *dev, int vector, int dest_id);
1453223ade2SPeter Xu void vtd_setup_ioapic_irq(struct pci_dev *dev, int vector,
1463223ade2SPeter Xu int dest_id, trigger_mode_t trigger);
14716c0b05fSPeter Xu
14816c0b05fSPeter Xu #endif
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