| /qemu/target/ppc/translate/ |
| H A D | vsx-ops.c.inc | 1 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
2 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
3 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
5 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
6 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
7 GEN_HANDLER_E(mfvsrld, 0X1F, 0x13, 0x09, 0x0000F800, PPC_NONE, PPC2_ISA300),
8 GEN_HANDLER_E(mtvsrdd, 0X1F, 0x13, 0x0D, 0x0, PPC_NONE, PPC2_ISA300),
9 GEN_HANDLER_E(mtvsrws, 0x1F, 0x13, 0x0C, 0x0000F800, PPC_NONE, PPC2_ISA300),
13 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
14 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
[all …]
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| H A D | spe-impl.c.inc | 130 tcg_gen_addi_i32(ret, arg1, 0x8000);
166 tcg_gen_andi_i32(t0, arg2, 0x3F);
171 tcg_gen_movi_i32(ret, 0);
182 tcg_gen_andi_i32(t0, arg2, 0x3F);
187 tcg_gen_movi_i32(ret, 0);
198 tcg_gen_andi_i32(t0, arg2, 0x3F);
203 tcg_gen_movi_i32(ret, 0);
210 tcg_gen_andi_i32(t0, arg2, 0x1F);
272 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
368 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
[all …]
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| /qemu/tests/tcg/aarch64/ |
| H A D | test-2248.c | 12 "and w11, w12, #0xff\n\t" in test()
13 "cmp w11, #0\n\t" in test()
14 "csetm x14, ne\n\t" in test()
15 "lsr x13, x14, %3\n\t" in test()
16 "sxtb %0, w13" in test()
19 : "x11", "x12", "x13", "x14"); in test()
25 long r = test(0, 1, 2); in main()
27 return 0; in main()
|
| H A D | fcvt.ref | 4 00 SINGLE: -nan / 0xffa00000 (0 => OK)
5 00 HALF: 0xff00 (0x1 => INVALID)
6 01 SINGLE: -nan / 0xffc00000 (0 => OK)
7 01 HALF: 0xfe00 (0 => OK)
8 02 SINGLE: -inf / 0xff800000 (0 => OK)
9 02 HALF: 0xfc00 (0 => OK)
10 03 SINGLE: -3.40282346638528859812e+38 / 0xff7fffff (0 => OK)
11 03 HALF: 0xfc00 (0x14 => OVERFLOW INEXACT )
12 04 SINGLE: -1.11100004769645909791e+31 / 0xf30c3a59 (0 => OK)
13 04 HALF: 0xfc00 (0x14 => OVERFLOW INEXACT )
[all …]
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| /qemu/tests/tcg/hexagon/ |
| H A D | hvx_histogram_input.h | 18 { 0x26, 0x32, 0x2e, 0x2e, 0x2d, 0x2c, 0x2d, 0x2d,
19 0x2c, 0x2e, 0x31, 0x33, 0x36, 0x39, 0x3b, 0x3f,
20 0x42, 0x46, 0x4a, 0x4c, 0x51, 0x53, 0x53, 0x54,
21 0x56, 0x57, 0x58, 0x57, 0x56, 0x52, 0x51, 0x4f,
22 0x4c, 0x49, 0x47, 0x42, 0x3e, 0x3b, 0x38, 0x35,
23 0x33, 0x30, 0x2e, 0x2c, 0x2b, 0x2a, 0x2a, 0x28,
24 0x28, 0x27, 0x27, 0x28, 0x29, 0x2a, 0x2c, 0x2e,
25 0x2f, 0x33, 0x36, 0x38, 0x3c, 0x3d, 0x40, 0x42,
26 0x43, 0x42, 0x43, 0x44, 0x43, 0x41, 0x40, 0x3b,
27 0x3b, 0x3a, 0x38, 0x35, 0x32, 0x2f, 0x2c, 0x29,
[all …]
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| /qemu/hw/block/ |
| H A D | cdrom.c | 34 buf[0] = (lba / 75) / 60; in lba_to_msf()
46 if (start_track > 1 && start_track != 0xaa) in cdrom_read_toc()
52 *q++ = 0; /* reserved */ in cdrom_read_toc()
53 *q++ = 0x14; /* ADR, control */ in cdrom_read_toc()
55 *q++ = 0; /* reserved */ in cdrom_read_toc()
57 *q++ = 0; /* reserved */ in cdrom_read_toc()
58 lba_to_msf(q, 0); in cdrom_read_toc()
61 /* sector 0 */ in cdrom_read_toc()
62 stl_be_p(q, 0); in cdrom_read_toc()
67 *q++ = 0; /* reserved */ in cdrom_read_toc()
[all …]
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| /qemu/disas/ |
| H A D | alpha.c | 65 #define AXP_OPCODE_BASE 0x0001 /* Base architecture -- all cpus. */
66 #define AXP_OPCODE_EV4 0x0002 /* EV4 specific PALcode insns. */
67 #define AXP_OPCODE_EV5 0x0004 /* EV5 specific PALcode insns. */
68 #define AXP_OPCODE_EV6 0x0008 /* EV6 specific PALcode insns. */
69 #define AXP_OPCODE_BWX 0x0100 /* Byte/word extension (amask bit 0). */
70 #define AXP_OPCODE_CIX 0x0200 /* "Count" extension (amask bit 1). */
71 #define AXP_OPCODE_MAX 0x0400 /* Multimedia extension (amask bit 8). */
76 #define AXP_OP(i) (((i) >> 26) & 0x3F)
79 #define AXP_NOPS 0x40
122 if ((o->flags & AXP_OPERAND_SIGNED) != 0
[all …]
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| H A D | sparc.c | 49 SPARC_OPCODE_ARCH_V6 = 0,
178 0 32/64 bit immediate for set or setx (v9) insns
185 #define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */
186 #define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */
187 #define OP(x) ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns. */
188 #define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */
189 #define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */
191 #define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */
195 #define DISP30(x) ((x) & 0x3fffffff)
196 #define ASI(x) (((x) & 0xff) << 5) /* Asi field of format3 insns. */
[all …]
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| /qemu/pc-bios/keymaps/ |
| H A D | sl | 3 Shift_R 0x36
4 Shift_L 0x2a
6 Alt_R 0xb8
7 Mode_switch 0xb8
8 ISO_Level3_Shift 0xb8
9 Alt_L 0x38
11 Control_R 0x9d
12 Control_L 0x1d
16 Super_R 0xdc
17 Super_L 0xdb
[all …]
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| /qemu/tests/bench/ |
| H A D | test_akcipher_keys.c.inc | 12 0x30, 0x82, 0x02, 0x5c, 0x02, 0x01, 0x00, 0x02,
13 0x81, 0x81, 0x00, 0xe6, 0x4d, 0x76, 0x4f, 0xb2,
14 0x97, 0x09, 0xad, 0x9d, 0x17, 0x33, 0xf2, 0x30,
15 0x42, 0x83, 0xa9, 0xcb, 0x49, 0xa4, 0x2e, 0x59,
16 0x5e, 0x75, 0x51, 0xd1, 0xac, 0xc8, 0x86, 0x3e,
17 0xdb, 0x72, 0x2e, 0xb2, 0xf7, 0xc3, 0x5b, 0xc7,
18 0xea, 0xed, 0x30, 0xd1, 0xf7, 0x37, 0xee, 0x9d,
19 0x36, 0x59, 0x6f, 0xf8, 0xce, 0xc0, 0x5c, 0x82,
20 0x80, 0x37, 0x83, 0xd7, 0x45, 0x6a, 0xe9, 0xea,
21 0xc5, 0x3a, 0x59, 0x6b, 0x34, 0x31, 0x44, 0x00,
[all …]
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| /qemu/hw/timer/ |
| H A D | sh_timer.c | 20 #define TIMER_TCR_TPSC (7 << 0)
26 #define TIMER_TCR_RESERVED (0x3f << 10)
28 #define TIMER_FEAT_CAPT (1 << 0)
31 #define OFFSET_TCOR 0
73 return s->tcr | (s->int_level ? TIMER_TCR_UNF : 0); in sh_timer_read()
79 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", in sh_timer_read()
81 return 0; in sh_timer_read()
93 ptimer_set_limit(s->timer, s->tcor, 0); in sh_timer_write()
114 case 0: in sh_timer_write()
140 case 0: in sh_timer_write()
[all …]
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| /qemu/tests/unit/ |
| H A D | test-crypto-der.c | 27 "\x30\x82\x01\x39" /* SEQUENCE, offset: 0, length: 313 */
46 "\x00\xd1\x75\xaf\x4b\xc6\x1a\xb0\x98\x14\x42\xae\x33\xf3\x44\xde"
60 "\x30\x82\x04\xa6" /* SEQUENCE, offset: 0, length 1190 */
69 "\xb2\x68\x0d\xe6\xc3\x5c\x2d\xf8\xa2\xbd\x00\x1a\xf6\xb6\xdd\x14"
83 "\x8a\xd2\xc2\x0a\x14\xa9\xb0\xd2\x68\x9f\x67\x5b\x1c\x3a\x03\xfe"
103 "\x77\x73\x08\x0f\x32\xbd\xe6\x95\xdc\xd0\x14\x7d\x44\xdc\x3e\xd9"
131 "\x4b\x69\xec\xf0\x5f\xf3\x88\x69\xcd\xbe\xed\x3c\xc5\x14\x5c\x0c"
146 "\x88\x14\x33\xe6\xbc\xca\x6b\x88\x90\x57\x3b\x0c\xa3\x6e\x47\xdf"
151 "\x30\x53" /* SEQUENCE, offset 0, length 83 */
164 "\x30\x77" /* SEQUENCE, offset 0, length 119 */
[all …]
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| H A D | test-crypto-akcipher.c | 29 0x30, 0x82, 0x02, 0x5c, 0x02, 0x01, 0x00, 0x02,
30 0x81, 0x81, 0x00, 0xe6, 0x4d, 0x76, 0x4f, 0xb2,
31 0x97, 0x09, 0xad, 0x9d, 0x17, 0x33, 0xf2, 0x30,
32 0x42, 0x83, 0xa9, 0xcb, 0x49, 0xa4, 0x2e, 0x59,
33 0x5e, 0x75, 0x51, 0xd1, 0xac, 0xc8, 0x86, 0x3e,
34 0xdb, 0x72, 0x2e, 0xb2, 0xf7, 0xc3, 0x5b, 0xc7,
35 0xea, 0xed, 0x30, 0xd1, 0xf7, 0x37, 0xee, 0x9d,
36 0x36, 0x59, 0x6f, 0xf8, 0xce, 0xc0, 0x5c, 0x82,
37 0x80, 0x37, 0x83, 0xd7, 0x45, 0x6a, 0xe9, 0xea,
38 0xc5, 0x3a, 0x59, 0x6b, 0x34, 0x31, 0x44, 0x00,
[all …]
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| /qemu/tests/qtest/ |
| H A D | xlnx-can-test.c | 31 #define CAN0_BASE_ADDR 0xFF060000
32 #define CAN1_BASE_ADDR 0xFF070000
35 #define R_SRR_OFFSET 0x00
36 #define R_MSR_OFFSET 0x04
37 #define R_SR_OFFSET 0x18
38 #define R_ISR_OFFSET 0x1C
39 #define R_ICR_OFFSET 0x24
40 #define R_TXID_OFFSET 0x30
41 #define R_TXDLC_OFFSET 0x34
42 #define R_TXDATA1_OFFSET 0x38
[all …]
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| /qemu/hw/display/ |
| H A D | cirrus_vga.c | 66 // sequencer 0x07
67 #define CIRRUS_SR7_BPP_VGA 0x00
68 #define CIRRUS_SR7_BPP_SVGA 0x01
69 #define CIRRUS_SR7_BPP_MASK 0x0e
70 #define CIRRUS_SR7_BPP_8 0x00
71 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
72 #define CIRRUS_SR7_BPP_24 0x04
73 #define CIRRUS_SR7_BPP_16 0x06
74 #define CIRRUS_SR7_BPP_32 0x08
75 #define CIRRUS_SR7_ISAADDR_MASK 0xe0
[all …]
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| H A D | vga_regs.h | 32 #define VGA_CRT_DC 0x3D5 /* CRT Controller Data Register - color emulation */
33 #define VGA_CRT_DM 0x3B5 /* CRT Controller Data Register - mono emulation */
34 #define VGA_ATT_R 0x3C1 /* Attribute Controller Data Read Register */
35 #define VGA_ATT_W 0x3C0 /* Attribute Controller Data Write Register */
36 #define VGA_GFX_D 0x3CF /* Graphics Controller Data Register */
37 #define VGA_SEQ_D 0x3C5 /* Sequencer Data Register */
38 #define VGA_MIS_R 0x3CC /* Misc Output Read Register */
39 #define VGA_MIS_W 0x3C2 /* Misc Output Write Register */
40 #define VGA_FTC_R 0x3CA /* Feature Control Read Register */
41 #define VGA_IS1_RC 0x3DA /* Input Status Register 1 - color emulation */
[all …]
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| /qemu/include/scsi/ |
| H A D | constants.h | 30 #define TEST_UNIT_READY 0x00
31 #define REWIND 0x01
32 #define REQUEST_SENSE 0x03
33 #define FORMAT_UNIT 0x04
34 #define READ_BLOCK_LIMITS 0x05
35 #define INITIALIZE_ELEMENT_STATUS 0x07
36 #define REASSIGN_BLOCKS 0x07
37 #define READ_6 0x08
38 #define WRITE_6 0x0a
39 #define SET_CAPACITY 0x0b
[all …]
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| /qemu/hw/rx/ |
| H A D | rx62n.c | 38 #define RX62N_IRAM_BASE 0x00000000
39 #define RX62N_DFLASH_BASE 0x00100000
40 #define RX62N_CFLASH_BASE 0xfff80000
46 #define RX62N_ICU_BASE 0x00087000
47 #define RX62N_TMR_BASE 0x00088200
48 #define RX62N_CMT_BASE 0x00088000
49 #define RX62N_SCI_BASE 0x00088240
79 * 0x00 - 0x91: IPR no (IPR00 to IPR91)
80 * 0xff: IPR not assigned
84 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
[all …]
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| /qemu/hw/char/ |
| H A D | sh_serial.c | 41 #define SH_SERIAL_FLAG_TEND (1 << 0)
83 memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH); in sh_serial_clear_fifo()
84 s->rx_cnt = 0; in sh_serial_clear_fifo()
85 s->rx_head = 0; in sh_serial_clear_fifo()
86 s->rx_tail = 0; in sh_serial_clear_fifo()
98 case 0x00: /* SMR */ in sh_serial_write()
99 s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff); in sh_serial_write()
101 case 0x04: /* BRR */ in sh_serial_write()
104 case 0x08: /* SCR */ in sh_serial_write()
105 /* TODO : For SH7751, SCIF mask should be 0xfb. */ in sh_serial_write()
[all …]
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| /qemu/include/hw/cxl/ |
| H A D | cxl_component.h | 14 #define CXL2_COMPONENT_IO_REGION_SIZE 0x1000
15 #define CXL2_COMPONENT_CM_REGION_SIZE 0x1000
16 #define CXL2_COMPONENT_BLOCK_SIZE 0x10000
43 REG32(CXL_CAPABILITY_HEADER, 0)
44 FIELD(CXL_CAPABILITY_HEADER, ID, 0, 16)
51 FIELD(CXL_##type##_CAPABILITY_HEADER, ID, 0, 16) \
54 CXLx_CAPABILITY_HEADER(RAS, 0x4)
55 CXLx_CAPABILITY_HEADER(LINK, 0x8)
56 CXLx_CAPABILITY_HEADER(HDM, 0xc)
57 CXLx_CAPABILITY_HEADER(EXTSEC, 0x10)
[all …]
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| /qemu/tests/tcg/arm/ |
| H A D | fcvt.ref | 4 00 SINGLE: -nan / 0xffa00000 (0 => OK)
5 00 HALF: 0xff00 (0x1 => INVALID)
6 01 SINGLE: -nan / 0xffc00000 (0 => OK)
7 01 HALF: 0xfe00 (0 => OK)
8 02 SINGLE: -inf / 0xff800000 (0 => OK)
9 02 HALF: 0xfc00 (0 => OK)
10 03 SINGLE: -3.40282346638528859812e+38 / 0xff7fffff (0 => OK)
11 03 HALF: 0xfc00 (0x14 => OVERFLOW INEXACT )
12 04 SINGLE: -1.11100004769645909791e+31 / 0xf30c3a59 (0 => OK)
13 04 HALF: 0xfc00 (0x14 => OVERFLOW INEXACT )
[all …]
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| /qemu/target/tricore/ |
| H A D | tricore-opcodes.h | 34 #define MASK_OP_MAJOR(op) MASK_BITS_SHIFT(op, 0, 7)
290 OPCM_16_SR_SYSTEM = 0x00,
291 OPCM_16_SR_ACCU = 0x32,
293 OPC1_16_SRC_ADD = 0xc2,
294 OPC1_16_SRC_ADD_A15 = 0x92,
295 OPC1_16_SRC_ADD_15A = 0x9a,
296 OPC1_16_SRR_ADD = 0x42,
297 OPC1_16_SRR_ADD_A15 = 0x12,
298 OPC1_16_SRR_ADD_15A = 0x1a,
299 OPC1_16_SRC_ADD_A = 0xb0,
[all …]
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| /qemu/hw/net/can/ |
| H A D | can_sja1000.h | 42 uint8_t mode; /* 0 .. Mode register, DS-p26 */
60 uint8_t control; /* 0 .. Control register */
75 SJA_MOD = 0x00, /* Mode control register */
76 SJA_CMR = 0x01, /* Command register */
77 SJA_SR = 0x02, /* Status register */
78 SJA_IR = 0x03, /* Interrupt register */
79 SJA_IER = 0x04, /* Interrupt Enable */
80 SJA_BTR0 = 0x06, /* Bus Timing register 0 */
81 SJA_BTR1 = 0x07, /* Bus Timing register 1 */
82 SJA_OCR = 0x08, /* Output Control register */
[all …]
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| /qemu/hw/gpio/ |
| H A D | mpc8xxx.c | 73 return 0; in mpc8xxx_gpio_read()
77 case 0x0: /* Direction */ in mpc8xxx_gpio_read()
79 case 0x4: /* Open Drain */ in mpc8xxx_gpio_read()
81 case 0x8: /* Data */ in mpc8xxx_gpio_read()
83 case 0xC: /* Interrupt Event */ in mpc8xxx_gpio_read()
85 case 0x10: /* Interrupt Mask */ in mpc8xxx_gpio_read()
87 case 0x14: /* Interrupt Control */ in mpc8xxx_gpio_read()
90 return 0; in mpc8xxx_gpio_read()
100 for (i = 0; i < 32; i++) { in mpc8xxx_write_data()
101 uint32_t mask = 0x80000000 >> i; in mpc8xxx_write_data()
[all …]
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| /qemu/hw/arm/ |
| H A D | omap1.c | 171 timer->val = 0; in omap_timer_fire()
172 timer->st = 0; in omap_timer_fire()
194 timer->rate = on ? omap_clk_getrate(timer->clk) : 0; in omap_timer_clk_update()
201 qemu_allocate_irq(omap_timer_clk_update, timer, 0)); in omap_timer_clk_setup()
215 case 0x00: /* CNTL_TIMER */ in omap_mpu_timer_read()
218 case 0x04: /* LOAD_TIM */ in omap_mpu_timer_read()
221 case 0x08: /* READ_TIM */ in omap_mpu_timer_read()
226 return 0; in omap_mpu_timer_read()
240 case 0x00: /* CNTL_TIMER */ in omap_mpu_timer_write()
249 case 0x04: /* LOAD_TIM */ in omap_mpu_timer_write()
[all …]
|