73         return 0;  in mpc8xxx_gpio_read()
77     case 0x0: /* Direction */  in mpc8xxx_gpio_read()
79     case 0x4: /* Open Drain */  in mpc8xxx_gpio_read()
81     case 0x8: /* Data */  in mpc8xxx_gpio_read()
83     case 0xC: /* Interrupt Event */  in mpc8xxx_gpio_read()
85     case 0x10: /* Interrupt Mask */  in mpc8xxx_gpio_read()
87     case 0x14: /* Interrupt Control */  in mpc8xxx_gpio_read()
90         return 0;  in mpc8xxx_gpio_read()
100     for (i = 0; i < 32; i++) {  in mpc8xxx_write_data()
101         uint32_t mask = 0x80000000 >> i;  in mpc8xxx_write_data()
108             qemu_set_irq(s->out[i], (new_data & mask) != 0);  in mpc8xxx_write_data()
126     case 0x0: /* Direction */  in mpc8xxx_gpio_write()
129     case 0x4: /* Open Drain */  in mpc8xxx_gpio_write()
132     case 0x8: /* Data */  in mpc8xxx_gpio_write()
135     case 0xC: /* Interrupt Event */  in mpc8xxx_gpio_write()
138     case 0x10: /* Interrupt Mask */  in mpc8xxx_gpio_write()
141     case 0x14: /* Interrupt Control */  in mpc8xxx_gpio_write()
153     s->dir = 0;  in mpc8xxx_gpio_reset()
154     s->odr = 0;  in mpc8xxx_gpio_reset()
155     s->dat = 0;  in mpc8xxx_gpio_reset()
156     s->ier = 0;  in mpc8xxx_gpio_reset()
157     s->imr = 0;  in mpc8xxx_gpio_reset()
158     s->icr = 0;  in mpc8xxx_gpio_reset()
166     mask = 0x80000000 >> irq;  in mpc8xxx_gpio_set_irq()
167     if ((s->dir & mask) == 0) {  in mpc8xxx_gpio_set_irq()
195                           s, "mpc8xxx_gpio", 0x1000);  in mpc8xxx_gpio_initfn()