Lines Matching +full:0 +full:x14
171 timer->val = 0; in omap_timer_fire()
172 timer->st = 0; in omap_timer_fire()
194 timer->rate = on ? omap_clk_getrate(timer->clk) : 0; in omap_timer_clk_update()
201 qemu_allocate_irq(omap_timer_clk_update, timer, 0)); in omap_timer_clk_setup()
215 case 0x00: /* CNTL_TIMER */ in omap_mpu_timer_read()
218 case 0x04: /* LOAD_TIM */ in omap_mpu_timer_read()
221 case 0x08: /* READ_TIM */ in omap_mpu_timer_read()
226 return 0; in omap_mpu_timer_read()
240 case 0x00: /* CNTL_TIMER */ in omap_mpu_timer_write()
249 case 0x04: /* LOAD_TIM */ in omap_mpu_timer_write()
253 case 0x08: /* READ_TIM */ in omap_mpu_timer_write()
271 s->enable = 0; in omap_mpu_timer_reset()
273 s->val = 0; in omap_mpu_timer_reset()
274 s->ptv = 0; in omap_mpu_timer_reset()
275 s->ar = 0; in omap_mpu_timer_reset()
276 s->st = 0; in omap_mpu_timer_reset()
294 "omap-mpu-timer", 0x100); in omap_mpu_timer_init()
321 case 0x00: /* CNTL_TIMER */ in omap_wd_timer_read()
325 case 0x04: /* READ_TIMER */ in omap_wd_timer_read()
328 case 0x08: /* TIMER_MODE */ in omap_wd_timer_read()
333 return 0; in omap_wd_timer_read()
347 case 0x00: /* CNTL_TIMER */ in omap_wd_timer_write()
356 case 0x04: /* LOAD_TIMER */ in omap_wd_timer_write()
357 s->timer.reset_val = value & 0xffff; in omap_wd_timer_write()
360 case 0x08: /* TIMER_MODE */ in omap_wd_timer_write()
364 if (s->last_wr == 0xf5) { in omap_wd_timer_write()
365 if ((value & 0xff) == 0xa0) { in omap_wd_timer_write()
367 s->mode = 0; in omap_wd_timer_write()
377 s->last_wr = value & 0xff; in omap_wd_timer_write()
398 s->reset = 0; in omap_wd_timer_reset()
401 s->timer.reset_val = 0xffff; in omap_wd_timer_reset()
402 s->timer.val = 0; in omap_wd_timer_reset()
403 s->timer.st = 0; in omap_wd_timer_reset()
404 s->timer.ptv = 0; in omap_wd_timer_reset()
405 s->timer.ar = 0; in omap_wd_timer_reset()
422 "omap-wd-timer", 0x100); in omap_wd_timer_init()
445 case 0x00: /* TVR */ in omap_os_timer_read()
448 case 0x04: /* TCR */ in omap_os_timer_read()
451 case 0x08: /* CR */ in omap_os_timer_read()
458 return 0; in omap_os_timer_read()
473 case 0x00: /* TVR */ in omap_os_timer_write()
474 s->timer.reset_val = value & 0x00ffffff; in omap_os_timer_write()
477 case 0x04: /* TCR */ in omap_os_timer_write()
481 case 0x08: /* CR */ in omap_os_timer_write()
506 s->timer.enable = 0; in omap_os_timer_reset()
507 s->timer.it_ena = 0; in omap_os_timer_reset()
508 s->timer.reset_val = 0x00ffffff; in omap_os_timer_reset()
509 s->timer.val = 0; in omap_os_timer_reset()
510 s->timer.st = 0; in omap_os_timer_reset()
511 s->timer.ptv = 0; in omap_os_timer_reset()
528 "omap-os-timer", 0x800); in omap_os_timer_init()
546 case 0x14: /* IT_STATUS */ in omap_ulpd_pm_read()
548 s->ulpd_pm_regs[addr >> 2] = 0; in omap_ulpd_pm_read()
552 case 0x18: /* Reserved */ in omap_ulpd_pm_read()
553 case 0x1c: /* Reserved */ in omap_ulpd_pm_read()
554 case 0x20: /* Reserved */ in omap_ulpd_pm_read()
555 case 0x28: /* Reserved */ in omap_ulpd_pm_read()
556 case 0x2c: /* Reserved */ in omap_ulpd_pm_read()
559 case 0x00: /* COUNTER_32_LSB */ in omap_ulpd_pm_read()
560 case 0x04: /* COUNTER_32_MSB */ in omap_ulpd_pm_read()
561 case 0x08: /* COUNTER_HIGH_FREQ_LSB */ in omap_ulpd_pm_read()
562 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ in omap_ulpd_pm_read()
563 case 0x10: /* GAUGING_CTRL */ in omap_ulpd_pm_read()
564 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ in omap_ulpd_pm_read()
565 case 0x30: /* CLOCK_CTRL */ in omap_ulpd_pm_read()
566 case 0x34: /* SOFT_REQ */ in omap_ulpd_pm_read()
567 case 0x38: /* COUNTER_32_FIQ */ in omap_ulpd_pm_read()
568 case 0x3c: /* DPLL_CTRL */ in omap_ulpd_pm_read()
569 case 0x40: /* STATUS_REQ */ in omap_ulpd_pm_read()
571 case 0x48: /* LOCL_TIME */ in omap_ulpd_pm_read()
572 case 0x4c: /* APLL_CTRL */ in omap_ulpd_pm_read()
573 case 0x50: /* POWER_CTRL */ in omap_ulpd_pm_read()
578 return 0; in omap_ulpd_pm_read()
593 if (diff & (1 << 0)) /* SOFT_DPLL_REQ */ in omap_ulpd_req_update()
594 omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1); in omap_ulpd_req_update()
618 case 0x00: /* COUNTER_32_LSB */ in omap_ulpd_pm_write()
619 case 0x04: /* COUNTER_32_MSB */ in omap_ulpd_pm_write()
620 case 0x08: /* COUNTER_HIGH_FREQ_LSB */ in omap_ulpd_pm_write()
621 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ in omap_ulpd_pm_write()
622 case 0x14: /* IT_STATUS */ in omap_ulpd_pm_write()
623 case 0x40: /* STATUS_REQ */ in omap_ulpd_pm_write()
627 case 0x10: /* GAUGING_CTRL */ in omap_ulpd_pm_write()
628 /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */ in omap_ulpd_pm_write()
639 s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff; in omap_ulpd_pm_write()
640 s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff; in omap_ulpd_pm_write()
642 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2; in omap_ulpd_pm_write()
646 s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff; in omap_ulpd_pm_write()
647 s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff; in omap_ulpd_pm_write()
649 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1; in omap_ulpd_pm_write()
651 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */ in omap_ulpd_pm_write()
658 case 0x18: /* Reserved */ in omap_ulpd_pm_write()
659 case 0x1c: /* Reserved */ in omap_ulpd_pm_write()
660 case 0x20: /* Reserved */ in omap_ulpd_pm_write()
661 case 0x28: /* Reserved */ in omap_ulpd_pm_write()
662 case 0x2c: /* Reserved */ in omap_ulpd_pm_write()
665 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ in omap_ulpd_pm_write()
666 case 0x38: /* COUNTER_32_FIQ */ in omap_ulpd_pm_write()
667 case 0x48: /* LOCL_TIME */ in omap_ulpd_pm_write()
668 case 0x50: /* POWER_CTRL */ in omap_ulpd_pm_write()
672 case 0x30: /* CLOCK_CTRL */ in omap_ulpd_pm_write()
674 s->ulpd_pm_regs[addr >> 2] = value & 0x3f; in omap_ulpd_pm_write()
678 case 0x34: /* SOFT_REQ */ in omap_ulpd_pm_write()
680 s->ulpd_pm_regs[addr >> 2] = value & 0x1f; in omap_ulpd_pm_write()
684 case 0x3c: /* DPLL_CTRL */ in omap_ulpd_pm_write()
690 s->ulpd_pm_regs[addr >> 2] = value & 0x2fff; in omap_ulpd_pm_write()
691 if (diff & (0x3ff << 2)) { in omap_ulpd_pm_write()
694 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ in omap_ulpd_pm_write()
704 (s->ulpd_pm_regs[addr >> 2] & 0xfffe) | in omap_ulpd_pm_write()
711 case 0x4c: /* APLL_CTRL */ in omap_ulpd_pm_write()
713 s->ulpd_pm_regs[addr >> 2] = value & 0xf; in omap_ulpd_pm_write()
714 if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */ in omap_ulpd_pm_write()
716 (value & (1 << 0)) ? "apll" : "dpll4")); in omap_ulpd_pm_write()
732 mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001; in omap_ulpd_pm_reset()
733 mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000; in omap_ulpd_pm_reset()
734 mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001; in omap_ulpd_pm_reset()
735 mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000; in omap_ulpd_pm_reset()
736 mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000; in omap_ulpd_pm_reset()
737 mpu->ulpd_pm_regs[0x18 >> 2] = 0x01; in omap_ulpd_pm_reset()
738 mpu->ulpd_pm_regs[0x1c >> 2] = 0x01; in omap_ulpd_pm_reset()
739 mpu->ulpd_pm_regs[0x20 >> 2] = 0x01; in omap_ulpd_pm_reset()
740 mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff; in omap_ulpd_pm_reset()
741 mpu->ulpd_pm_regs[0x28 >> 2] = 0x01; in omap_ulpd_pm_reset()
742 mpu->ulpd_pm_regs[0x2c >> 2] = 0x01; in omap_ulpd_pm_reset()
743 omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000); in omap_ulpd_pm_reset()
744 mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000; in omap_ulpd_pm_reset()
745 omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000); in omap_ulpd_pm_reset()
746 mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000; in omap_ulpd_pm_reset()
747 mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001; in omap_ulpd_pm_reset()
748 mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211; in omap_ulpd_pm_reset()
749 mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */ in omap_ulpd_pm_reset()
750 mpu->ulpd_pm_regs[0x48 >> 2] = 0x960; in omap_ulpd_pm_reset()
751 mpu->ulpd_pm_regs[0x4c >> 2] = 0x08; in omap_ulpd_pm_reset()
752 mpu->ulpd_pm_regs[0x50 >> 2] = 0x08; in omap_ulpd_pm_reset()
762 "omap-ulpd-pm", 0x800); in omap_ulpd_pm_init()
778 case 0x00: /* FUNC_MUX_CTRL_0 */ in omap_pin_cfg_read()
779 case 0x04: /* FUNC_MUX_CTRL_1 */ in omap_pin_cfg_read()
780 case 0x08: /* FUNC_MUX_CTRL_2 */ in omap_pin_cfg_read()
783 case 0x0c: /* COMP_MODE_CTRL_0 */ in omap_pin_cfg_read()
784 return s->comp_mode_ctrl[0]; in omap_pin_cfg_read()
786 case 0x10: /* FUNC_MUX_CTRL_3 */ in omap_pin_cfg_read()
787 case 0x14: /* FUNC_MUX_CTRL_4 */ in omap_pin_cfg_read()
788 case 0x18: /* FUNC_MUX_CTRL_5 */ in omap_pin_cfg_read()
789 case 0x1c: /* FUNC_MUX_CTRL_6 */ in omap_pin_cfg_read()
790 case 0x20: /* FUNC_MUX_CTRL_7 */ in omap_pin_cfg_read()
791 case 0x24: /* FUNC_MUX_CTRL_8 */ in omap_pin_cfg_read()
792 case 0x28: /* FUNC_MUX_CTRL_9 */ in omap_pin_cfg_read()
793 case 0x2c: /* FUNC_MUX_CTRL_A */ in omap_pin_cfg_read()
794 case 0x30: /* FUNC_MUX_CTRL_B */ in omap_pin_cfg_read()
795 case 0x34: /* FUNC_MUX_CTRL_C */ in omap_pin_cfg_read()
796 case 0x38: /* FUNC_MUX_CTRL_D */ in omap_pin_cfg_read()
799 case 0x40: /* PULL_DWN_CTRL_0 */ in omap_pin_cfg_read()
800 case 0x44: /* PULL_DWN_CTRL_1 */ in omap_pin_cfg_read()
801 case 0x48: /* PULL_DWN_CTRL_2 */ in omap_pin_cfg_read()
802 case 0x4c: /* PULL_DWN_CTRL_3 */ in omap_pin_cfg_read()
803 return s->pull_dwn_ctrl[(addr & 0xf) >> 2]; in omap_pin_cfg_read()
805 case 0x50: /* GATE_INH_CTRL_0 */ in omap_pin_cfg_read()
806 return s->gate_inh_ctrl[0]; in omap_pin_cfg_read()
808 case 0x60: /* VOLTAGE_CTRL_0 */ in omap_pin_cfg_read()
809 return s->voltage_ctrl[0]; in omap_pin_cfg_read()
811 case 0x70: /* TEST_DBG_CTRL_0 */ in omap_pin_cfg_read()
812 return s->test_dbg_ctrl[0]; in omap_pin_cfg_read()
814 case 0x80: /* MOD_CONF_CTRL_0 */ in omap_pin_cfg_read()
815 return s->mod_conf_ctrl[0]; in omap_pin_cfg_read()
819 return 0; in omap_pin_cfg_read()
891 case 0x00: /* FUNC_MUX_CTRL_0 */ in omap_pin_cfg_write()
897 case 0x04: /* FUNC_MUX_CTRL_1 */ in omap_pin_cfg_write()
903 case 0x08: /* FUNC_MUX_CTRL_2 */ in omap_pin_cfg_write()
907 case 0x0c: /* COMP_MODE_CTRL_0 */ in omap_pin_cfg_write()
908 s->comp_mode_ctrl[0] = value; in omap_pin_cfg_write()
909 s->compat1509 = (value != 0x0000eaef); in omap_pin_cfg_write()
910 omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]); in omap_pin_cfg_write()
911 omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]); in omap_pin_cfg_write()
914 case 0x10: /* FUNC_MUX_CTRL_3 */ in omap_pin_cfg_write()
915 case 0x14: /* FUNC_MUX_CTRL_4 */ in omap_pin_cfg_write()
916 case 0x18: /* FUNC_MUX_CTRL_5 */ in omap_pin_cfg_write()
917 case 0x1c: /* FUNC_MUX_CTRL_6 */ in omap_pin_cfg_write()
918 case 0x20: /* FUNC_MUX_CTRL_7 */ in omap_pin_cfg_write()
919 case 0x24: /* FUNC_MUX_CTRL_8 */ in omap_pin_cfg_write()
920 case 0x28: /* FUNC_MUX_CTRL_9 */ in omap_pin_cfg_write()
921 case 0x2c: /* FUNC_MUX_CTRL_A */ in omap_pin_cfg_write()
922 case 0x30: /* FUNC_MUX_CTRL_B */ in omap_pin_cfg_write()
923 case 0x34: /* FUNC_MUX_CTRL_C */ in omap_pin_cfg_write()
924 case 0x38: /* FUNC_MUX_CTRL_D */ in omap_pin_cfg_write()
928 case 0x40: /* PULL_DWN_CTRL_0 */ in omap_pin_cfg_write()
929 case 0x44: /* PULL_DWN_CTRL_1 */ in omap_pin_cfg_write()
930 case 0x48: /* PULL_DWN_CTRL_2 */ in omap_pin_cfg_write()
931 case 0x4c: /* PULL_DWN_CTRL_3 */ in omap_pin_cfg_write()
932 s->pull_dwn_ctrl[(addr & 0xf) >> 2] = value; in omap_pin_cfg_write()
935 case 0x50: /* GATE_INH_CTRL_0 */ in omap_pin_cfg_write()
936 s->gate_inh_ctrl[0] = value; in omap_pin_cfg_write()
939 case 0x60: /* VOLTAGE_CTRL_0 */ in omap_pin_cfg_write()
940 s->voltage_ctrl[0] = value; in omap_pin_cfg_write()
943 case 0x70: /* TEST_DBG_CTRL_0 */ in omap_pin_cfg_write()
944 s->test_dbg_ctrl[0] = value; in omap_pin_cfg_write()
947 case 0x80: /* MOD_CONF_CTRL_0 */ in omap_pin_cfg_write()
948 diff = s->mod_conf_ctrl[0] ^ value; in omap_pin_cfg_write()
949 s->mod_conf_ctrl[0] = value; in omap_pin_cfg_write()
968 omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0); in omap_pin_cfg_reset()
969 omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0); in omap_pin_cfg_reset()
970 omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0); in omap_pin_cfg_reset()
971 memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl)); in omap_pin_cfg_reset()
972 memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl)); in omap_pin_cfg_reset()
973 memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl)); in omap_pin_cfg_reset()
974 memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl)); in omap_pin_cfg_reset()
975 memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl)); in omap_pin_cfg_reset()
976 memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl)); in omap_pin_cfg_reset()
977 memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl)); in omap_pin_cfg_reset()
985 "omap-pin-cfg", 0x800); in omap_pin_cfg_init()
1001 case 0xfffe1800: /* DIE_ID_LSB */ in omap_id_read()
1002 return 0xc9581f0e; in omap_id_read()
1003 case 0xfffe1804: /* DIE_ID_MSB */ in omap_id_read()
1004 return 0xa8858bfa; in omap_id_read()
1006 case 0xfffe2000: /* PRODUCT_ID_LSB */ in omap_id_read()
1007 return 0x00aaaafc; in omap_id_read()
1008 case 0xfffe2004: /* PRODUCT_ID_MSB */ in omap_id_read()
1009 return 0xcafeb574; in omap_id_read()
1011 case 0xfffed400: /* JTAG_ID_LSB */ in omap_id_read()
1014 return 0x03310315; in omap_id_read()
1016 return 0x03310115; in omap_id_read()
1022 case 0xfffed404: /* JTAG_ID_MSB */ in omap_id_read()
1025 return 0xfb57402f; in omap_id_read()
1027 return 0xfb47002f; in omap_id_read()
1035 return 0; in omap_id_read()
1058 "omap-id", 0x100000000ULL); in omap_id_init()
1060 0xfffe1800, 0x800); in omap_id_init()
1061 memory_region_add_subregion(memory, 0xfffe1800, &mpu->id_iomem_e18); in omap_id_init()
1063 0xfffed400, 0x100); in omap_id_init()
1064 memory_region_add_subregion(memory, 0xfffed400, &mpu->id_iomem_ed4); in omap_id_init()
1067 &mpu->id_iomem, 0xfffe2000, 0x800); in omap_id_init()
1068 memory_region_add_subregion(memory, 0xfffe2000, &mpu->id_iomem_e20); in omap_id_init()
1083 case 0x00: /* CTRL */ in omap_mpui_read()
1085 case 0x04: /* DEBUG_ADDR */ in omap_mpui_read()
1086 return 0x01ffffff; in omap_mpui_read()
1087 case 0x08: /* DEBUG_DATA */ in omap_mpui_read()
1088 return 0xffffffff; in omap_mpui_read()
1089 case 0x0c: /* DEBUG_FLAG */ in omap_mpui_read()
1090 return 0x00000800; in omap_mpui_read()
1091 case 0x10: /* STATUS */ in omap_mpui_read()
1092 return 0x00000000; in omap_mpui_read()
1095 case 0x14: /* DSP_STATUS */ in omap_mpui_read()
1096 case 0x18: /* DSP_BOOT_CONFIG */ in omap_mpui_read()
1097 return 0x00000000; in omap_mpui_read()
1098 case 0x1c: /* DSP_MPUI_CONFIG */ in omap_mpui_read()
1099 return 0x0000ffff; in omap_mpui_read()
1103 return 0; in omap_mpui_read()
1117 case 0x00: /* CTRL */ in omap_mpui_write()
1118 s->mpui_ctrl = value & 0x007fffff; in omap_mpui_write()
1121 case 0x04: /* DEBUG_ADDR */ in omap_mpui_write()
1122 case 0x08: /* DEBUG_DATA */ in omap_mpui_write()
1123 case 0x0c: /* DEBUG_FLAG */ in omap_mpui_write()
1124 case 0x10: /* STATUS */ in omap_mpui_write()
1126 case 0x14: /* DSP_STATUS */ in omap_mpui_write()
1129 case 0x18: /* DSP_BOOT_CONFIG */ in omap_mpui_write()
1130 case 0x1c: /* DSP_MPUI_CONFIG */ in omap_mpui_write()
1146 s->mpui_ctrl = 0x0003ff1b; in omap_mpui_reset()
1153 "omap-mpui", 0x100); in omap_mpui_init()
1181 case 0x00: /* TIPB_CNTL */ in omap_tipb_bridge_read()
1183 case 0x04: /* TIPB_BUS_ALLOC */ in omap_tipb_bridge_read()
1185 case 0x08: /* MPU_TIPB_CNTL */ in omap_tipb_bridge_read()
1187 case 0x0c: /* ENHANCED_TIPB_CNTL */ in omap_tipb_bridge_read()
1189 case 0x10: /* ADDRESS_DBG */ in omap_tipb_bridge_read()
1190 case 0x14: /* DATA_DEBUG_LOW */ in omap_tipb_bridge_read()
1191 case 0x18: /* DATA_DEBUG_HIGH */ in omap_tipb_bridge_read()
1192 return 0xffff; in omap_tipb_bridge_read()
1193 case 0x1c: /* DEBUG_CNTR_SIG */ in omap_tipb_bridge_read()
1194 return 0x00f8; in omap_tipb_bridge_read()
1198 return 0; in omap_tipb_bridge_read()
1212 case 0x00: /* TIPB_CNTL */ in omap_tipb_bridge_write()
1213 s->control = value & 0xffff; in omap_tipb_bridge_write()
1216 case 0x04: /* TIPB_BUS_ALLOC */ in omap_tipb_bridge_write()
1217 s->alloc = value & 0x003f; in omap_tipb_bridge_write()
1220 case 0x08: /* MPU_TIPB_CNTL */ in omap_tipb_bridge_write()
1221 s->buffer = value & 0x0003; in omap_tipb_bridge_write()
1224 case 0x0c: /* ENHANCED_TIPB_CNTL */ in omap_tipb_bridge_write()
1226 s->enh_control = value & 0x000f; in omap_tipb_bridge_write()
1229 case 0x10: /* ADDRESS_DBG */ in omap_tipb_bridge_write()
1230 case 0x14: /* DATA_DEBUG_LOW */ in omap_tipb_bridge_write()
1231 case 0x18: /* DATA_DEBUG_HIGH */ in omap_tipb_bridge_write()
1232 case 0x1c: /* DEBUG_CNTR_SIG */ in omap_tipb_bridge_write()
1249 s->control = 0xffff; in omap_tipb_bridge_reset()
1250 s->alloc = 0x0009; in omap_tipb_bridge_reset()
1251 s->buffer = 0x0000; in omap_tipb_bridge_reset()
1252 s->enh_control = 0x000f; in omap_tipb_bridge_reset()
1265 "omap-tipb-bridge", 0x100); in omap_tipb_bridge_init()
1283 case 0x00: /* IMIF_PRIO */ in omap_tcmi_read()
1284 case 0x04: /* EMIFS_PRIO */ in omap_tcmi_read()
1285 case 0x08: /* EMIFF_PRIO */ in omap_tcmi_read()
1286 case 0x0c: /* EMIFS_CONFIG */ in omap_tcmi_read()
1287 case 0x10: /* EMIFS_CS0_CONFIG */ in omap_tcmi_read()
1288 case 0x14: /* EMIFS_CS1_CONFIG */ in omap_tcmi_read()
1289 case 0x18: /* EMIFS_CS2_CONFIG */ in omap_tcmi_read()
1290 case 0x1c: /* EMIFS_CS3_CONFIG */ in omap_tcmi_read()
1291 case 0x24: /* EMIFF_MRS */ in omap_tcmi_read()
1292 case 0x28: /* TIMEOUT1 */ in omap_tcmi_read()
1293 case 0x2c: /* TIMEOUT2 */ in omap_tcmi_read()
1294 case 0x30: /* TIMEOUT3 */ in omap_tcmi_read()
1295 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ in omap_tcmi_read()
1296 case 0x40: /* EMIFS_CFG_DYN_WAIT */ in omap_tcmi_read()
1299 case 0x20: /* EMIFF_SDRAM_CONFIG */ in omap_tcmi_read()
1307 return 0; in omap_tcmi_read()
1321 case 0x00: /* IMIF_PRIO */ in omap_tcmi_write()
1322 case 0x04: /* EMIFS_PRIO */ in omap_tcmi_write()
1323 case 0x08: /* EMIFF_PRIO */ in omap_tcmi_write()
1324 case 0x10: /* EMIFS_CS0_CONFIG */ in omap_tcmi_write()
1325 case 0x14: /* EMIFS_CS1_CONFIG */ in omap_tcmi_write()
1326 case 0x18: /* EMIFS_CS2_CONFIG */ in omap_tcmi_write()
1327 case 0x1c: /* EMIFS_CS3_CONFIG */ in omap_tcmi_write()
1328 case 0x20: /* EMIFF_SDRAM_CONFIG */ in omap_tcmi_write()
1329 case 0x24: /* EMIFF_MRS */ in omap_tcmi_write()
1330 case 0x28: /* TIMEOUT1 */ in omap_tcmi_write()
1331 case 0x2c: /* TIMEOUT2 */ in omap_tcmi_write()
1332 case 0x30: /* TIMEOUT3 */ in omap_tcmi_write()
1333 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ in omap_tcmi_write()
1334 case 0x40: /* EMIFS_CFG_DYN_WAIT */ in omap_tcmi_write()
1337 case 0x0c: /* EMIFS_CONFIG */ in omap_tcmi_write()
1338 s->tcmi_regs[addr >> 2] = (value & 0xf) | (1 << 4); in omap_tcmi_write()
1354 mpu->tcmi_regs[0x00 >> 2] = 0x00000000; in omap_tcmi_reset()
1355 mpu->tcmi_regs[0x04 >> 2] = 0x00000000; in omap_tcmi_reset()
1356 mpu->tcmi_regs[0x08 >> 2] = 0x00000000; in omap_tcmi_reset()
1357 mpu->tcmi_regs[0x0c >> 2] = 0x00000010; in omap_tcmi_reset()
1358 mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb; in omap_tcmi_reset()
1359 mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb; in omap_tcmi_reset()
1360 mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb; in omap_tcmi_reset()
1361 mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb; in omap_tcmi_reset()
1362 mpu->tcmi_regs[0x20 >> 2] = 0x00618800; in omap_tcmi_reset()
1363 mpu->tcmi_regs[0x24 >> 2] = 0x00000037; in omap_tcmi_reset()
1364 mpu->tcmi_regs[0x28 >> 2] = 0x00000000; in omap_tcmi_reset()
1365 mpu->tcmi_regs[0x2c >> 2] = 0x00000000; in omap_tcmi_reset()
1366 mpu->tcmi_regs[0x30 >> 2] = 0x00000000; in omap_tcmi_reset()
1367 mpu->tcmi_regs[0x3c >> 2] = 0x00000003; in omap_tcmi_reset()
1368 mpu->tcmi_regs[0x40 >> 2] = 0x00000000; in omap_tcmi_reset()
1375 "omap-tcmi", 0x100); in omap_tcmi_init()
1396 if (addr == 0x00) /* CTL_REG */ in omap_dpll_read()
1400 return 0; in omap_dpll_read()
1416 if (addr == 0x00) { /* CTL_REG */ in omap_dpll_write()
1419 s->mode = value & 0x2fff; in omap_dpll_write()
1420 if (diff & (0x3ff << 2)) { in omap_dpll_write()
1423 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ in omap_dpll_write()
1432 s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1); in omap_dpll_write()
1449 s->mode = 0x2002; in omap_dpll_reset()
1457 memory_region_init_io(&s->iomem, NULL, &omap_dpll_ops, s, "omap-dpll", 0x100); in omap_dpll_init()
1477 case 0x00: /* ARM_CKCTL */ in omap_clkm_read()
1480 case 0x04: /* ARM_IDLECT1 */ in omap_clkm_read()
1483 case 0x08: /* ARM_IDLECT2 */ in omap_clkm_read()
1486 case 0x0c: /* ARM_EWUPCT */ in omap_clkm_read()
1489 case 0x10: /* ARM_RSTCT1 */ in omap_clkm_read()
1492 case 0x14: /* ARM_RSTCT2 */ in omap_clkm_read()
1495 case 0x18: /* ARM_SYSST */ in omap_clkm_read()
1498 case 0x1c: /* ARM_CKOUT1 */ in omap_clkm_read()
1501 case 0x20: /* ARM_CKOUT2 */ in omap_clkm_read()
1506 return 0; in omap_clkm_read()
1550 if (diff & (3 << 0)) { /* PERDIV */ in omap_clkm_ckctl_update()
1552 omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1); in omap_clkm_ckctl_update()
1574 SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */ in omap_clkm_idlect1_update()
1600 SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */ in omap_clkm_idlect2_update()
1630 omap_clk_onoff(clk, 0); in omap_clkm_ckout1_update()
1636 case 0: in omap_clkm_ckout1_update()
1650 if (diff & (3 << 0)) { /* ACLKOUT */ in omap_clkm_ckout1_update()
1652 switch ((value >> 0) & 3) { in omap_clkm_ckout1_update()
1666 omap_clk_onoff(clk, 0); in omap_clkm_ckout1_update()
1688 case 0x00: /* ARM_CKCTL */ in omap_clkm_write()
1690 s->clkm.arm_ckctl = value & 0x7fff; in omap_clkm_write()
1694 case 0x04: /* ARM_IDLECT1 */ in omap_clkm_write()
1696 s->clkm.arm_idlect1 = value & 0x0fff; in omap_clkm_write()
1700 case 0x08: /* ARM_IDLECT2 */ in omap_clkm_write()
1702 s->clkm.arm_idlect2 = value & 0x07ff; in omap_clkm_write()
1706 case 0x0c: /* ARM_EWUPCT */ in omap_clkm_write()
1707 s->clkm.arm_ewupct = value & 0x003f; in omap_clkm_write()
1710 case 0x10: /* ARM_RSTCT1 */ in omap_clkm_write()
1712 s->clkm.arm_rstct1 = value & 0x0007; in omap_clkm_write()
1715 s->clkm.cold_start = 0xa; in omap_clkm_write()
1728 case 0x14: /* ARM_RSTCT2 */ in omap_clkm_write()
1729 s->clkm.arm_rstct2 = value & 0x0001; in omap_clkm_write()
1732 case 0x18: /* ARM_SYSST */ in omap_clkm_write()
1738 s->clkm.cold_start &= value & 0x3f; in omap_clkm_write()
1741 case 0x1c: /* ARM_CKOUT1 */ in omap_clkm_write()
1743 s->clkm.arm_ckout1 = value & 0x003f; in omap_clkm_write()
1747 case 0x20: /* ARM_CKOUT2 */ in omap_clkm_write()
1770 case 0x04: /* DSP_IDLECT1 */ in omap_clkdsp_read()
1773 case 0x08: /* DSP_IDLECT2 */ in omap_clkdsp_read()
1776 case 0x14: /* DSP_RSTCT2 */ in omap_clkdsp_read()
1779 case 0x18: /* DSP_SYSST */ in omap_clkdsp_read()
1785 return 0; in omap_clkdsp_read()
1816 case 0x04: /* DSP_IDLECT1 */ in omap_clkdsp_write()
1818 s->clkm.dsp_idlect1 = value & 0x01f7; in omap_clkdsp_write()
1822 case 0x08: /* DSP_IDLECT2 */ in omap_clkdsp_write()
1823 s->clkm.dsp_idlect2 = value & 0x0037; in omap_clkdsp_write()
1828 case 0x14: /* DSP_RSTCT2 */ in omap_clkdsp_write()
1829 s->clkm.dsp_rstct2 = value & 0x0001; in omap_clkdsp_write()
1832 case 0x18: /* DSP_SYSST */ in omap_clkdsp_write()
1833 s->clkm.cold_start &= value & 0x3f; in omap_clkdsp_write()
1850 s->clkm.cold_start = 0x6; in omap_clkm_reset()
1851 s->clkm.clocking_scheme = 0; in omap_clkm_reset()
1852 omap_clkm_ckctl_update(s, ~0, 0x3000); in omap_clkm_reset()
1853 s->clkm.arm_ckctl = 0x3000; in omap_clkm_reset()
1854 omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400); in omap_clkm_reset()
1855 s->clkm.arm_idlect1 = 0x0400; in omap_clkm_reset()
1856 omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100); in omap_clkm_reset()
1857 s->clkm.arm_idlect2 = 0x0100; in omap_clkm_reset()
1858 s->clkm.arm_ewupct = 0x003f; in omap_clkm_reset()
1859 s->clkm.arm_rstct1 = 0x0000; in omap_clkm_reset()
1860 s->clkm.arm_rstct2 = 0x0000; in omap_clkm_reset()
1861 s->clkm.arm_ckout1 = 0x0015; in omap_clkm_reset()
1862 s->clkm.dpll1_mode = 0x2002; in omap_clkm_reset()
1863 omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040); in omap_clkm_reset()
1864 s->clkm.dsp_idlect1 = 0x0040; in omap_clkm_reset()
1865 omap_clkdsp_idlect2_update(s, ~0, 0x0000); in omap_clkm_reset()
1866 s->clkm.dsp_idlect2 = 0x0000; in omap_clkm_reset()
1867 s->clkm.dsp_rstct2 = 0x0000; in omap_clkm_reset()
1874 "omap-clkm", 0x100); in omap_clkm_init()
1876 "omap-clkdsp", 0x1000); in omap_clkm_init()
1878 s->clkm.arm_idlect1 = 0x03ff; in omap_clkm_init()
1879 s->clkm.arm_idlect2 = 0x0100; in omap_clkm_init()
1880 s->clkm.dsp_idlect1 = 0x0002; in omap_clkm_init()
1882 s->clkm.cold_start = 0x3a; in omap_clkm_init()
1931 if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */ in omap_mpuio_set()
1940 uint8_t *row, rows = 0, cols = ~s->cols; in omap_mpuio_kbd_update()
1962 case 0x00: /* INPUT_LATCH */ in omap_mpuio_read()
1965 case 0x04: /* OUTPUT_REG */ in omap_mpuio_read()
1968 case 0x08: /* IO_CNTL */ in omap_mpuio_read()
1971 case 0x10: /* KBR_LATCH */ in omap_mpuio_read()
1974 case 0x14: /* KBC_REG */ in omap_mpuio_read()
1977 case 0x18: /* GPIO_EVENT_MODE_REG */ in omap_mpuio_read()
1980 case 0x1c: /* GPIO_INT_EDGE_REG */ in omap_mpuio_read()
1983 case 0x20: /* KBD_INT */ in omap_mpuio_read()
1984 return (~s->row_latch & 0x1f) && !s->kbd_mask; in omap_mpuio_read()
1986 case 0x24: /* GPIO_INT */ in omap_mpuio_read()
1993 case 0x28: /* KBD_MASKIT */ in omap_mpuio_read()
1996 case 0x2c: /* GPIO_MASKIT */ in omap_mpuio_read()
1999 case 0x30: /* GPIO_DEBOUNCING_REG */ in omap_mpuio_read()
2002 case 0x34: /* GPIO_LATCH_REG */ in omap_mpuio_read()
2007 return 0; in omap_mpuio_read()
2024 case 0x04: /* OUTPUT_REG */ in omap_mpuio_write()
2034 case 0x08: /* IO_CNTL */ in omap_mpuio_write()
2046 case 0x14: /* KBC_REG */ in omap_mpuio_write()
2051 case 0x18: /* GPIO_EVENT_MODE_REG */ in omap_mpuio_write()
2052 s->event = value & 0x1f; in omap_mpuio_write()
2055 case 0x1c: /* GPIO_INT_EDGE_REG */ in omap_mpuio_write()
2059 case 0x28: /* KBD_MASKIT */ in omap_mpuio_write()
2064 case 0x2c: /* GPIO_MASKIT */ in omap_mpuio_write()
2068 case 0x30: /* GPIO_DEBOUNCING_REG */ in omap_mpuio_write()
2069 s->debounce = value & 0x1ff; in omap_mpuio_write()
2072 case 0x00: /* INPUT_LATCH */ in omap_mpuio_write()
2073 case 0x10: /* KBR_LATCH */ in omap_mpuio_write()
2074 case 0x20: /* KBD_INT */ in omap_mpuio_write()
2075 case 0x24: /* GPIO_INT */ in omap_mpuio_write()
2076 case 0x34: /* GPIO_LATCH_REG */ in omap_mpuio_write()
2094 s->inputs = 0; in omap_mpuio_reset()
2095 s->outputs = 0; in omap_mpuio_reset()
2096 s->dir = ~0; in omap_mpuio_reset()
2097 s->event = 0; in omap_mpuio_reset()
2098 s->edge = 0; in omap_mpuio_reset()
2099 s->kbd_mask = 0; in omap_mpuio_reset()
2100 s->mask = 0; in omap_mpuio_reset()
2101 s->debounce = 0; in omap_mpuio_reset()
2102 s->latch = 0; in omap_mpuio_reset()
2103 s->ints = 0; in omap_mpuio_reset()
2104 s->row_latch = 0x1f; in omap_mpuio_reset()
2131 "omap-mpuio", 0x800); in omap_mpuio_init()
2134 omap_clk_adduser(clk, qemu_allocate_irq(omap_mpuio_onoff, s, 0)); in omap_mpuio_init()
2146 if (line >= 16 || line < 0) in omap_mpuio_out_set()
2153 if (row >= 5 || row < 0) in omap_mpuio_key()
2181 if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */ in omap_uwire_transfer_start()
2183 qemu_log_mask(LOG_UNIMP, "uWireSlave TX CS:%d data:0x%04x\n", in omap_uwire_transfer_start()
2185 s->txbuf >> (16 - ((s->control >> 5) & 0x1f))); in omap_uwire_transfer_start()
2188 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or in omap_uwire_transfer_start()
2192 if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */ in omap_uwire_transfer_start()
2197 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or in omap_uwire_transfer_start()
2212 case 0x00: /* RDR */ in omap_uwire_read()
2216 case 0x04: /* CSR */ in omap_uwire_read()
2219 case 0x08: /* SR1 */ in omap_uwire_read()
2220 return s->setup[0]; in omap_uwire_read()
2221 case 0x0c: /* SR2 */ in omap_uwire_read()
2223 case 0x10: /* SR3 */ in omap_uwire_read()
2225 case 0x14: /* SR4 */ in omap_uwire_read()
2227 case 0x18: /* SR5 */ in omap_uwire_read()
2232 return 0; in omap_uwire_read()
2247 case 0x00: /* TDR */ in omap_uwire_write()
2257 case 0x04: /* CSR */ in omap_uwire_write()
2258 s->control = value & 0x1fff; in omap_uwire_write()
2263 case 0x08: /* SR1 */ in omap_uwire_write()
2264 s->setup[0] = value & 0x003f; in omap_uwire_write()
2267 case 0x0c: /* SR2 */ in omap_uwire_write()
2268 s->setup[1] = value & 0x0fc0; in omap_uwire_write()
2271 case 0x10: /* SR3 */ in omap_uwire_write()
2272 s->setup[2] = value & 0x0003; in omap_uwire_write()
2275 case 0x14: /* SR4 */ in omap_uwire_write()
2276 s->setup[3] = value & 0x0001; in omap_uwire_write()
2279 case 0x18: /* SR5 */ in omap_uwire_write()
2280 s->setup[4] = value & 0x000f; in omap_uwire_write()
2297 s->control = 0; in omap_uwire_reset()
2298 s->setup[0] = 0; in omap_uwire_reset()
2299 s->setup[1] = 0; in omap_uwire_reset()
2300 s->setup[2] = 0; in omap_uwire_reset()
2301 s->setup[3] = 0; in omap_uwire_reset()
2302 s->setup[4] = 0; in omap_uwire_reset()
2318 memory_region_init_io(&s->iomem, NULL, &omap_uwire_ops, s, "omap-uwire", 0x800); in omap_uwire_init()
2335 int output = (s->clk && s->enable) ? s->level : 0; in omap_pwl_update()
2353 case 0x00: /* PWL_LEVEL */ in omap_pwl_read()
2355 case 0x04: /* PWL_CTRL */ in omap_pwl_read()
2359 return 0; in omap_pwl_read()
2374 case 0x00: /* PWL_LEVEL */ in omap_pwl_write()
2378 case 0x04: /* PWL_CTRL */ in omap_pwl_write()
2396 s->output = 0; in omap_pwl_reset()
2397 s->level = 0; in omap_pwl_reset()
2398 s->enable = 0; in omap_pwl_reset()
2420 "omap-pwl", 0x800); in omap_pwl_init()
2423 omap_clk_adduser(clk, qemu_allocate_irq(omap_pwl_clk_update, s, 0)); in omap_pwl_init()
2446 case 0x00: /* FRC */ in omap_pwt_read()
2448 case 0x04: /* VCR */ in omap_pwt_read()
2450 case 0x08: /* GCR */ in omap_pwt_read()
2454 return 0; in omap_pwt_read()
2469 case 0x00: /* FRC */ in omap_pwt_write()
2470 s->frc = value & 0x3f; in omap_pwt_write()
2472 case 0x04: /* VRC */ in omap_pwt_write()
2495 s->vrc = value & 0x7f; in omap_pwt_write()
2497 case 0x08: /* GCR */ in omap_pwt_write()
2514 s->frc = 0; in omap_pwt_reset()
2515 s->vrc = 0; in omap_pwt_reset()
2516 s->gcr = 0; in omap_pwt_reset()
2528 "omap-pwt", 0x800); in omap_pwt_init()
2580 case 0x00: /* SECONDS_REG */ in omap_rtc_read()
2583 case 0x04: /* MINUTES_REG */ in omap_rtc_read()
2586 case 0x08: /* HOURS_REG */ in omap_rtc_read()
2593 case 0x0c: /* DAYS_REG */ in omap_rtc_read()
2596 case 0x10: /* MONTHS_REG */ in omap_rtc_read()
2599 case 0x14: /* YEARS_REG */ in omap_rtc_read()
2602 case 0x18: /* WEEK_REG */ in omap_rtc_read()
2605 case 0x20: /* ALARM_SECONDS_REG */ in omap_rtc_read()
2608 case 0x24: /* ALARM_MINUTES_REG */ in omap_rtc_read()
2611 case 0x28: /* ALARM_HOURS_REG */ in omap_rtc_read()
2618 case 0x2c: /* ALARM_DAYS_REG */ in omap_rtc_read()
2621 case 0x30: /* ALARM_MONTHS_REG */ in omap_rtc_read()
2624 case 0x34: /* ALARM_YEARS_REG */ in omap_rtc_read()
2627 case 0x40: /* RTC_CTRL_REG */ in omap_rtc_read()
2631 case 0x44: /* RTC_STATUS_REG */ in omap_rtc_read()
2633 s->status &= ~0x3d; in omap_rtc_read()
2636 case 0x48: /* RTC_INTERRUPTS_REG */ in omap_rtc_read()
2639 case 0x4c: /* RTC_COMP_LSB_REG */ in omap_rtc_read()
2640 return ((uint16_t) s->comp_reg) & 0xff; in omap_rtc_read()
2642 case 0x50: /* RTC_COMP_MSB_REG */ in omap_rtc_read()
2647 return 0; in omap_rtc_read()
2664 case 0x00: /* SECONDS_REG */ in omap_rtc_write()
2669 case 0x04: /* MINUTES_REG */ in omap_rtc_write()
2674 case 0x08: /* HOURS_REG */ in omap_rtc_write()
2677 s->ti += (from_bcd(value & 0x3f) & 12) * 3600; in omap_rtc_write()
2680 s->ti += from_bcd(value & 0x3f) * 3600; in omap_rtc_write()
2683 case 0x0c: /* DAYS_REG */ in omap_rtc_write()
2688 case 0x10: /* MONTHS_REG */ in omap_rtc_write()
2691 ti[0] = mktimegm(&s->current_tm); in omap_rtc_write()
2694 if (ti[0] != -1 && ti[1] != -1) { in omap_rtc_write()
2695 s->ti -= ti[0]; in omap_rtc_write()
2704 case 0x14: /* YEARS_REG */ in omap_rtc_write()
2707 ti[0] = mktimegm(&s->current_tm); in omap_rtc_write()
2710 if (ti[0] != -1 && ti[1] != -1) { in omap_rtc_write()
2711 s->ti -= ti[0]; in omap_rtc_write()
2720 case 0x18: /* WEEK_REG */ in omap_rtc_write()
2723 case 0x20: /* ALARM_SECONDS_REG */ in omap_rtc_write()
2728 case 0x24: /* ALARM_MINUTES_REG */ in omap_rtc_write()
2733 case 0x28: /* ALARM_HOURS_REG */ in omap_rtc_write()
2736 ((from_bcd(value & 0x3f)) % 12) + in omap_rtc_write()
2743 case 0x2c: /* ALARM_DAYS_REG */ in omap_rtc_write()
2748 case 0x30: /* ALARM_MONTHS_REG */ in omap_rtc_write()
2753 case 0x34: /* ALARM_YEARS_REG */ in omap_rtc_write()
2758 case 0x40: /* RTC_CTRL_REG */ in omap_rtc_write()
2763 s->status &= 0xfd; in omap_rtc_write()
2767 case 0x44: /* RTC_STATUS_REG */ in omap_rtc_write()
2768 s->status &= ~((value & 0xc0) ^ 0x80); in omap_rtc_write()
2772 case 0x48: /* RTC_INTERRUPTS_REG */ in omap_rtc_write()
2776 case 0x4c: /* RTC_COMP_LSB_REG */ in omap_rtc_write()
2777 s->comp_reg &= 0xff00; in omap_rtc_write()
2778 s->comp_reg |= 0x00ff & value; in omap_rtc_write()
2781 case 0x50: /* RTC_COMP_MSB_REG */ in omap_rtc_write()
2782 s->comp_reg &= 0x00ff; in omap_rtc_write()
2783 s->comp_reg |= 0xff00 & (value << 8); in omap_rtc_write()
2809 s->round = 0; in omap_rtc_tick()
2814 if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) { in omap_rtc_tick()
2815 s->status |= 0x40; in omap_rtc_tick()
2819 if (s->interrupts & 0x04) in omap_rtc_tick()
2821 case 0: in omap_rtc_tick()
2822 s->status |= 0x04; in omap_rtc_tick()
2828 s->status |= 0x08; in omap_rtc_tick()
2834 s->status |= 0x10; in omap_rtc_tick()
2841 s->status |= 0x20; in omap_rtc_tick()
2865 s->interrupts = 0; in omap_rtc_reset()
2866 s->comp_reg = 0; in omap_rtc_reset()
2867 s->running = 0; in omap_rtc_reset()
2868 s->pm_am = 0; in omap_rtc_reset()
2869 s->auto_comp = 0; in omap_rtc_reset()
2870 s->round = 0; in omap_rtc_reset()
2872 memset(&s->alarm_tm, 0, sizeof(s->alarm_tm)); in omap_rtc_reset()
2873 s->alarm_tm.tm_mday = 0x01; in omap_rtc_reset()
2875 qemu_get_timedate(&tm, 0); in omap_rtc_reset()
2896 "omap-rtc", 0x800); in omap_rtc_init()
2932 switch ((s->spcr[0] >> 4) & 3) { /* RINTM */ in omap_mcbsp_intr_update()
2933 case 0: in omap_mcbsp_intr_update()
2934 irq = (s->spcr[0] >> 1) & 1; /* RRDY */ in omap_mcbsp_intr_update()
2937 irq = (s->spcr[0] >> 3) & 1; /* RSYNCERR */ in omap_mcbsp_intr_update()
2940 irq = 0; in omap_mcbsp_intr_update()
2948 case 0: in omap_mcbsp_intr_update()
2955 irq = 0; in omap_mcbsp_intr_update()
2965 if ((s->spcr[0] >> 1) & 1) /* RRDY */ in omap_mcbsp_rx_newdata()
2966 s->spcr[0] |= 1 << 2; /* RFULL */ in omap_mcbsp_rx_newdata()
2967 s->spcr[0] |= 1 << 1; /* RRDY */ in omap_mcbsp_rx_newdata()
2975 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; in omap_mcbsp_source_tick()
2983 s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7]; in omap_mcbsp_source_tick()
3007 s->spcr[0] &= ~(1 << 1); /* RRDY */ in omap_mcbsp_rx_done()
3022 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; in omap_mcbsp_sink_tick()
3030 s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7]; in omap_mcbsp_sink_tick()
3058 s->tx_req = 0; in omap_mcbsp_tx_stop()
3066 int rx_rate = 0, tx_rate = 0; in omap_mcbsp_req_update()
3071 if (s->spcr[0] & (1 << 0)) { /* RRST */ in omap_mcbsp_req_update()
3076 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ in omap_mcbsp_req_update()
3082 if (s->spcr[1] & (1 << 0)) { /* XRST */ in omap_mcbsp_req_update()
3087 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ in omap_mcbsp_req_update()
3124 case 0x00: /* DRR2 */ in omap_mcbsp_read()
3125 if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */ in omap_mcbsp_read()
3126 return 0x0000; in omap_mcbsp_read()
3128 case 0x02: /* DRR1 */ in omap_mcbsp_read()
3139 ret = 0x0000; in omap_mcbsp_read()
3144 return 0x0000; in omap_mcbsp_read()
3146 case 0x04: /* DXR2 */ in omap_mcbsp_read()
3147 case 0x06: /* DXR1 */ in omap_mcbsp_read()
3148 return 0x0000; in omap_mcbsp_read()
3150 case 0x08: /* SPCR2 */ in omap_mcbsp_read()
3152 case 0x0a: /* SPCR1 */ in omap_mcbsp_read()
3153 return s->spcr[0]; in omap_mcbsp_read()
3154 case 0x0c: /* RCR2 */ in omap_mcbsp_read()
3156 case 0x0e: /* RCR1 */ in omap_mcbsp_read()
3157 return s->rcr[0]; in omap_mcbsp_read()
3158 case 0x10: /* XCR2 */ in omap_mcbsp_read()
3160 case 0x12: /* XCR1 */ in omap_mcbsp_read()
3161 return s->xcr[0]; in omap_mcbsp_read()
3162 case 0x14: /* SRGR2 */ in omap_mcbsp_read()
3164 case 0x16: /* SRGR1 */ in omap_mcbsp_read()
3165 return s->srgr[0]; in omap_mcbsp_read()
3166 case 0x18: /* MCR2 */ in omap_mcbsp_read()
3168 case 0x1a: /* MCR1 */ in omap_mcbsp_read()
3169 return s->mcr[0]; in omap_mcbsp_read()
3170 case 0x1c: /* RCERA */ in omap_mcbsp_read()
3171 return s->rcer[0]; in omap_mcbsp_read()
3172 case 0x1e: /* RCERB */ in omap_mcbsp_read()
3174 case 0x20: /* XCERA */ in omap_mcbsp_read()
3175 return s->xcer[0]; in omap_mcbsp_read()
3176 case 0x22: /* XCERB */ in omap_mcbsp_read()
3178 case 0x24: /* PCR0 */ in omap_mcbsp_read()
3180 case 0x26: /* RCERC */ in omap_mcbsp_read()
3182 case 0x28: /* RCERD */ in omap_mcbsp_read()
3184 case 0x2a: /* XCERC */ in omap_mcbsp_read()
3186 case 0x2c: /* XCERD */ in omap_mcbsp_read()
3188 case 0x2e: /* RCERE */ in omap_mcbsp_read()
3190 case 0x30: /* RCERF */ in omap_mcbsp_read()
3192 case 0x32: /* XCERE */ in omap_mcbsp_read()
3194 case 0x34: /* XCERF */ in omap_mcbsp_read()
3196 case 0x36: /* RCERG */ in omap_mcbsp_read()
3198 case 0x38: /* RCERH */ in omap_mcbsp_read()
3200 case 0x3a: /* XCERG */ in omap_mcbsp_read()
3202 case 0x3c: /* XCERH */ in omap_mcbsp_read()
3207 return 0; in omap_mcbsp_read()
3217 case 0x00: /* DRR2 */ in omap_mcbsp_writeh()
3218 case 0x02: /* DRR1 */ in omap_mcbsp_writeh()
3222 case 0x04: /* DXR2 */ in omap_mcbsp_writeh()
3223 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ in omap_mcbsp_writeh()
3226 case 0x06: /* DXR1 */ in omap_mcbsp_writeh()
3230 s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff; in omap_mcbsp_writeh()
3231 s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff; in omap_mcbsp_writeh()
3240 case 0x08: /* SPCR2 */ in omap_mcbsp_writeh()
3241 s->spcr[1] &= 0x0002; in omap_mcbsp_writeh()
3242 s->spcr[1] |= 0x03f9 & value; in omap_mcbsp_writeh()
3243 s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */ in omap_mcbsp_writeh()
3248 case 0x0a: /* SPCR1 */ in omap_mcbsp_writeh()
3249 s->spcr[0] &= 0x0006; in omap_mcbsp_writeh()
3250 s->spcr[0] |= 0xf8f9 & value; in omap_mcbsp_writeh()
3257 s->spcr[0] &= ~6; in omap_mcbsp_writeh()
3258 s->rx_req = 0; in omap_mcbsp_writeh()
3264 case 0x0c: /* RCR2 */ in omap_mcbsp_writeh()
3265 s->rcr[1] = value & 0xffff; in omap_mcbsp_writeh()
3267 case 0x0e: /* RCR1 */ in omap_mcbsp_writeh()
3268 s->rcr[0] = value & 0x7fe0; in omap_mcbsp_writeh()
3270 case 0x10: /* XCR2 */ in omap_mcbsp_writeh()
3271 s->xcr[1] = value & 0xffff; in omap_mcbsp_writeh()
3273 case 0x12: /* XCR1 */ in omap_mcbsp_writeh()
3274 s->xcr[0] = value & 0x7fe0; in omap_mcbsp_writeh()
3276 case 0x14: /* SRGR2 */ in omap_mcbsp_writeh()
3277 s->srgr[1] = value & 0xffff; in omap_mcbsp_writeh()
3280 case 0x16: /* SRGR1 */ in omap_mcbsp_writeh()
3281 s->srgr[0] = value & 0xffff; in omap_mcbsp_writeh()
3284 case 0x18: /* MCR2 */ in omap_mcbsp_writeh()
3285 s->mcr[1] = value & 0x03e3; in omap_mcbsp_writeh()
3292 case 0x1a: /* MCR1 */ in omap_mcbsp_writeh()
3293 s->mcr[0] = value & 0x03e1; in omap_mcbsp_writeh()
3300 case 0x1c: /* RCERA */ in omap_mcbsp_writeh()
3301 s->rcer[0] = value & 0xffff; in omap_mcbsp_writeh()
3303 case 0x1e: /* RCERB */ in omap_mcbsp_writeh()
3304 s->rcer[1] = value & 0xffff; in omap_mcbsp_writeh()
3306 case 0x20: /* XCERA */ in omap_mcbsp_writeh()
3307 s->xcer[0] = value & 0xffff; in omap_mcbsp_writeh()
3309 case 0x22: /* XCERB */ in omap_mcbsp_writeh()
3310 s->xcer[1] = value & 0xffff; in omap_mcbsp_writeh()
3312 case 0x24: /* PCR0 */ in omap_mcbsp_writeh()
3313 s->pcr = value & 0x7faf; in omap_mcbsp_writeh()
3315 case 0x26: /* RCERC */ in omap_mcbsp_writeh()
3316 s->rcer[2] = value & 0xffff; in omap_mcbsp_writeh()
3318 case 0x28: /* RCERD */ in omap_mcbsp_writeh()
3319 s->rcer[3] = value & 0xffff; in omap_mcbsp_writeh()
3321 case 0x2a: /* XCERC */ in omap_mcbsp_writeh()
3322 s->xcer[2] = value & 0xffff; in omap_mcbsp_writeh()
3324 case 0x2c: /* XCERD */ in omap_mcbsp_writeh()
3325 s->xcer[3] = value & 0xffff; in omap_mcbsp_writeh()
3327 case 0x2e: /* RCERE */ in omap_mcbsp_writeh()
3328 s->rcer[4] = value & 0xffff; in omap_mcbsp_writeh()
3330 case 0x30: /* RCERF */ in omap_mcbsp_writeh()
3331 s->rcer[5] = value & 0xffff; in omap_mcbsp_writeh()
3333 case 0x32: /* XCERE */ in omap_mcbsp_writeh()
3334 s->xcer[4] = value & 0xffff; in omap_mcbsp_writeh()
3336 case 0x34: /* XCERF */ in omap_mcbsp_writeh()
3337 s->xcer[5] = value & 0xffff; in omap_mcbsp_writeh()
3339 case 0x36: /* RCERG */ in omap_mcbsp_writeh()
3340 s->rcer[6] = value & 0xffff; in omap_mcbsp_writeh()
3342 case 0x38: /* RCERH */ in omap_mcbsp_writeh()
3343 s->rcer[7] = value & 0xffff; in omap_mcbsp_writeh()
3345 case 0x3a: /* XCERG */ in omap_mcbsp_writeh()
3346 s->xcer[6] = value & 0xffff; in omap_mcbsp_writeh()
3348 case 0x3c: /* XCERH */ in omap_mcbsp_writeh()
3349 s->xcer[7] = value & 0xffff; in omap_mcbsp_writeh()
3362 if (offset == 0x04) { /* DXR */ in omap_mcbsp_writew()
3363 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ in omap_mcbsp_writew()
3369 (value >> 24) & 0xff; in omap_mcbsp_writew()
3371 (value >> 16) & 0xff; in omap_mcbsp_writew()
3373 (value >> 8) & 0xff; in omap_mcbsp_writew()
3375 (value >> 0) & 0xff; in omap_mcbsp_writew()
3411 memset(&s->spcr, 0, sizeof(s->spcr)); in omap_mcbsp_reset()
3412 memset(&s->rcr, 0, sizeof(s->rcr)); in omap_mcbsp_reset()
3413 memset(&s->xcr, 0, sizeof(s->xcr)); in omap_mcbsp_reset()
3414 s->srgr[0] = 0x0001; in omap_mcbsp_reset()
3415 s->srgr[1] = 0x2000; in omap_mcbsp_reset()
3416 memset(&s->mcr, 0, sizeof(s->mcr)); in omap_mcbsp_reset()
3417 memset(&s->pcr, 0, sizeof(s->pcr)); in omap_mcbsp_reset()
3418 memset(&s->rcer, 0, sizeof(s->rcer)); in omap_mcbsp_reset()
3419 memset(&s->xcer, 0, sizeof(s->xcer)); in omap_mcbsp_reset()
3420 s->tx_req = 0; in omap_mcbsp_reset()
3421 s->rx_req = 0; in omap_mcbsp_reset()
3422 s->tx_rate = 0; in omap_mcbsp_reset()
3423 s->rx_rate = 0; in omap_mcbsp_reset()
3437 s->txdrq = dma[0]; in omap_mcbsp_init()
3443 memory_region_init_io(&s->iomem, NULL, &omap_mcbsp_ops, s, "omap-mcbsp", 0x800); in omap_mcbsp_init()
3472 slave->rx_swallow = qemu_allocate_irq(omap_mcbsp_i2s_swallow, s, 0); in omap_mcbsp_i2s_attach()
3473 slave->tx_start = qemu_allocate_irq(omap_mcbsp_i2s_start, s, 0); in omap_mcbsp_i2s_attach()
3508 on = 0; in omap_lpg_update()
3515 per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */ in omap_lpg_update()
3521 } else if (on == 0 && s->on) { in omap_lpg_update()
3524 s->cycle = 0; in omap_lpg_update()
3537 s->control = 0x00; in omap_lpg_reset()
3538 s->power = 0x00; in omap_lpg_reset()
3553 case 0x00: /* LCR */ in omap_lpg_read()
3556 case 0x04: /* PMR */ in omap_lpg_read()
3561 return 0; in omap_lpg_read()
3576 case 0x00: /* LCR */ in omap_lpg_write()
3579 s->control = value & 0xff; in omap_lpg_write()
3583 case 0x04: /* PMR */ in omap_lpg_write()
3584 s->power = value & 0x01; in omap_lpg_write()
3617 memory_region_init_io(&s->iomem, NULL, &omap_lpg_ops, s, "omap-lpg", 0x800); in omap_lpg_init()
3620 omap_clk_adduser(clk, qemu_allocate_irq(omap_lpg_clk_update, s, 0)); in omap_lpg_init()
3634 return 0xfe4d; in omap_mpui_io_read()
3637 return 0; in omap_mpui_io_read()
3657 "omap-mpui-io", 0x7fff); in omap_setup_mpui_io()
3668 omap_mpu_timer_reset(mpu->timer[0]); in omap1_mpu_reset()
3679 omap_dpll_reset(mpu->dpll[0]); in omap1_mpu_reset()
3682 omap_uart_reset(mpu->uart[0]); in omap1_mpu_reset()
3693 omap_lpg_reset(mpu->led[0]); in omap1_mpu_reset()
3705 /* Strobe 0 */
3706 { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */
3707 { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */
3708 { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */
3709 { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */
3710 { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */
3711 { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */
3712 { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */
3713 { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */
3714 { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */
3715 { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */
3716 { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */
3717 { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */
3718 { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */
3719 { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */
3720 { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */
3721 { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */
3722 { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */
3724 { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */
3726 { 0 }
3753 { 0, OMAP_INT_DMA_CH0_6 },
3754 { 0, OMAP_INT_DMA_CH1_7 },
3755 { 0, OMAP_INT_DMA_CH2_8 },
3756 { 0, OMAP_INT_DMA_CH3 },
3757 { 0, OMAP_INT_DMA_CH4 },
3758 { 0, OMAP_INT_DMA_CH5 },
3794 return range_covers_byte(0xfffb0000, 0xffff0000 - 0xfffb0000, addr); in omap_validate_tipb_addr()
3800 return range_covers_byte(OMAP_LOCALBUS_BASE, 0x1000000, addr); in omap_validate_local_addr()
3806 return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr); in omap_validate_tipb_mpui_addr()
3825 s->wakeup = qemu_allocate_irq(omap_mpu_wakeup, s, 0); in omap310_mpu_init()
3835 omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s); in omap310_mpu_init()
3837 s->ih[0] = qdev_new("omap-intc"); in omap310_mpu_init()
3838 qdev_prop_set_uint32(s->ih[0], "size", 0x100); in omap310_mpu_init()
3839 omap_intc_set_iclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "arminth_ck")); in omap310_mpu_init()
3840 busdev = SYS_BUS_DEVICE(s->ih[0]); in omap310_mpu_init()
3842 sysbus_connect_irq(busdev, 0, in omap310_mpu_init()
3846 sysbus_mmio_map(busdev, 0, 0xfffecb00); in omap310_mpu_init()
3848 qdev_prop_set_uint32(s->ih[1], "size", 0x800); in omap310_mpu_init()
3852 sysbus_connect_irq(busdev, 0, in omap310_mpu_init()
3853 qdev_get_gpio_in(s->ih[0], OMAP_INT_15XX_IH2_IRQ)); in omap310_mpu_init()
3855 sysbus_mmio_map(busdev, 0, 0xfffe0000); in omap310_mpu_init()
3857 for (i = 0; i < 6; i++) { in omap310_mpu_init()
3861 s->dma = omap_dma_init(0xfffed800, dma_irqs, system_memory, in omap310_mpu_init()
3862 qdev_get_gpio_in(s->ih[0], OMAP_INT_DMA_LCD), in omap310_mpu_init()
3878 s->timer[0] = omap_mpu_timer_init(system_memory, 0xfffec500, in omap310_mpu_init()
3879 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER1), in omap310_mpu_init()
3881 s->timer[1] = omap_mpu_timer_init(system_memory, 0xfffec600, in omap310_mpu_init()
3882 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER2), in omap310_mpu_init()
3884 s->timer[2] = omap_mpu_timer_init(system_memory, 0xfffec700, in omap310_mpu_init()
3885 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER3), in omap310_mpu_init()
3888 s->wdt = omap_wd_timer_init(system_memory, 0xfffec800, in omap310_mpu_init()
3889 qdev_get_gpio_in(s->ih[0], OMAP_INT_WD_TIMER), in omap310_mpu_init()
3892 s->os_timer = omap_os_timer_init(system_memory, 0xfffb9000, in omap310_mpu_init()
3896 s->lcd = omap_lcdc_init(system_memory, 0xfffec000, in omap310_mpu_init()
3897 qdev_get_gpio_in(s->ih[0], OMAP_INT_LCD_CTRL), in omap310_mpu_init()
3901 omap_ulpd_pm_init(system_memory, 0xfffe0800, s); in omap310_mpu_init()
3902 omap_pin_cfg_init(system_memory, 0xfffe1000, s); in omap310_mpu_init()
3905 omap_mpui_init(system_memory, 0xfffec900, s); in omap310_mpu_init()
3907 s->private_tipb = omap_tipb_bridge_init(system_memory, 0xfffeca00, in omap310_mpu_init()
3908 qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PRIV), in omap310_mpu_init()
3910 s->public_tipb = omap_tipb_bridge_init(system_memory, 0xfffed300, in omap310_mpu_init()
3911 qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PUB), in omap310_mpu_init()
3914 omap_tcmi_init(system_memory, 0xfffecc00, s); in omap310_mpu_init()
3916 s->uart[0] = omap_uart_init(0xfffb0000, in omap310_mpu_init()
3922 serial_hd(0)); in omap310_mpu_init()
3923 s->uart[1] = omap_uart_init(0xfffb0800, in omap310_mpu_init()
3929 serial_hd(0) ? serial_hd(1) : NULL); in omap310_mpu_init()
3930 s->uart[2] = omap_uart_init(0xfffb9800, in omap310_mpu_init()
3931 qdev_get_gpio_in(s->ih[0], OMAP_INT_UART3), in omap310_mpu_init()
3936 serial_hd(0) && serial_hd(1) ? serial_hd(2) : NULL); in omap310_mpu_init()
3938 s->dpll[0] = omap_dpll_init(system_memory, 0xfffecf00, in omap310_mpu_init()
3940 s->dpll[1] = omap_dpll_init(system_memory, 0xfffed000, in omap310_mpu_init()
3942 s->dpll[2] = omap_dpll_init(system_memory, 0xfffed100, in omap310_mpu_init()
3945 dinfo = drive_get(IF_SD, 0, 0); in omap310_mpu_init()
3954 memory_region_add_subregion(system_memory, 0xfffb7800, in omap310_mpu_init()
3955 sysbus_mmio_get_region(SYS_BUS_DEVICE(s->mmc), 0)); in omap310_mpu_init()
3956 qdev_connect_gpio_out_named(s->mmc, "dma-tx", 0, s->drq[OMAP_DMA_MMC_TX]); in omap310_mpu_init()
3957 qdev_connect_gpio_out_named(s->mmc, "dma-rx", 0, s->drq[OMAP_DMA_MMC_RX]); in omap310_mpu_init()
3958 sysbus_connect_irq(SYS_BUS_DEVICE(s->mmc), 0, in omap310_mpu_init()
3969 s->mpuio = omap_mpuio_init(system_memory, 0xfffb5000, in omap310_mpu_init()
3978 sysbus_connect_irq(SYS_BUS_DEVICE(s->gpio), 0, in omap310_mpu_init()
3979 qdev_get_gpio_in(s->ih[0], OMAP_INT_GPIO_BANK1)); in omap310_mpu_init()
3980 sysbus_mmio_map(SYS_BUS_DEVICE(s->gpio), 0, 0xfffce000); in omap310_mpu_init()
3982 s->microwire = omap_uwire_init(system_memory, 0xfffb3000, in omap310_mpu_init()
3987 s->pwl = omap_pwl_init(system_memory, 0xfffb5800, in omap310_mpu_init()
3989 s->pwt = omap_pwt_init(system_memory, 0xfffb6000, in omap310_mpu_init()
3992 s->i2c[0] = qdev_new("omap_i2c"); in omap310_mpu_init()
3993 qdev_prop_set_uint8(s->i2c[0], "revision", 0x11); in omap310_mpu_init()
3994 omap_i2c_set_fclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "mpuper_ck")); in omap310_mpu_init()
3995 busdev = SYS_BUS_DEVICE(s->i2c[0]); in omap310_mpu_init()
3997 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C)); in omap310_mpu_init()
4000 sysbus_mmio_map(busdev, 0, 0xfffb3800); in omap310_mpu_init()
4002 s->rtc = omap_rtc_init(system_memory, 0xfffb4800, in omap310_mpu_init()
4007 s->mcbsp1 = omap_mcbsp_init(system_memory, 0xfffb1800, in omap310_mpu_init()
4011 s->mcbsp2 = omap_mcbsp_init(system_memory, 0xfffb1000, in omap310_mpu_init()
4012 qdev_get_gpio_in(s->ih[0], in omap310_mpu_init()
4014 qdev_get_gpio_in(s->ih[0], in omap310_mpu_init()
4017 s->mcbsp3 = omap_mcbsp_init(system_memory, 0xfffb7000, in omap310_mpu_init()
4022 s->led[0] = omap_lpg_init(system_memory, in omap310_mpu_init()
4023 0xfffbd000, omap_findclk(s, "clk32-kHz")); in omap310_mpu_init()
4025 0xfffbd800, omap_findclk(s, "clk32-kHz")); in omap310_mpu_init()