20 #define TIMER_TCR_TPSC          (7 << 0)
26 #define TIMER_TCR_RESERVED      (0x3f << 10)
28 #define TIMER_FEAT_CAPT   (1 << 0)
31 #define OFFSET_TCOR   0
73         return s->tcr | (s->int_level ? TIMER_TCR_UNF : 0);  in sh_timer_read()
79     qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",  in sh_timer_read()
81     return 0;  in sh_timer_read()
93         ptimer_set_limit(s->timer, s->tcor, 0);  in sh_timer_write()
114         case 0:  in sh_timer_write()
140         case 0:  in sh_timer_write()
154         case 0:  in sh_timer_write()
166         if ((value & TIMER_TCR_UNF) == 0) {  in sh_timer_write()
167             s->int_level = 0;  in sh_timer_write()
184         ptimer_set_limit(s->timer, s->tcor, 0);  in sh_timer_write()
188             ptimer_run(s->timer, 0);  in sh_timer_write()
200                       "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset);  in sh_timer_write()
215         ptimer_run(s->timer, 0);  in sh_timer_start_stop()
235     s->tcor = 0xffffffff;  in sh_timer_init()
236     s->tcnt = 0xffffffff;  in sh_timer_init()
237     s->tcpr = 0xdeadbeef;  in sh_timer_init()
238     s->tcr = 0;  in sh_timer_init()
239     s->enabled = 0;  in sh_timer_init()
268     if (offset >= 0x20) {  in tmu012_read()
271                           "%s: Bad channel offset 0x%" HWADDR_PRIx "\n",  in tmu012_read()
274         return sh_timer_read(s->timer[2], offset - 0x20);  in tmu012_read()
277     if (offset >= 0x14) {  in tmu012_read()
278         return sh_timer_read(s->timer[1], offset - 0x14);  in tmu012_read()
280     if (offset >= 0x08) {  in tmu012_read()
281         return sh_timer_read(s->timer[0], offset - 0x08);  in tmu012_read()
286     if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) {  in tmu012_read()
291                   "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset);  in tmu012_read()
292     return 0;  in tmu012_read()
301     if (offset >= 0x20) {  in tmu012_write()
304                           "%s: Bad channel offset 0x%" HWADDR_PRIx "\n",  in tmu012_write()
307         sh_timer_write(s->timer[2], offset - 0x20, value);  in tmu012_write()
311     if (offset >= 0x14) {  in tmu012_write()
312         sh_timer_write(s->timer[1], offset - 0x14, value);  in tmu012_write()
316     if (offset >= 0x08) {  in tmu012_write()
317         sh_timer_write(s->timer[0], offset - 0x08, value);  in tmu012_write()
322         sh_timer_start_stop(s->timer[0], value & (1 << 0));  in tmu012_write()
336     if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) {  in tmu012_write()
337         s->tocr = value & (1 << 0);  in tmu012_write()
352     int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0;  in tmu012_init()
356     s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq);  in tmu012_init()
363     memory_region_init_io(&s->iomem, NULL, &tmu012_ops, s, "timer", 0x30);  in tmu012_init()
366                              &s->iomem, 0, memory_region_size(&s->iomem));  in tmu012_init()
370                              &s->iomem, 0, memory_region_size(&s->iomem));  in tmu012_init()