Lines Matching +full:0 +full:x14
14 #define CXL2_COMPONENT_IO_REGION_SIZE 0x1000
15 #define CXL2_COMPONENT_CM_REGION_SIZE 0x1000
16 #define CXL2_COMPONENT_BLOCK_SIZE 0x10000
43 REG32(CXL_CAPABILITY_HEADER, 0)
44 FIELD(CXL_CAPABILITY_HEADER, ID, 0, 16)
51 FIELD(CXL_##type##_CAPABILITY_HEADER, ID, 0, 16) \
54 CXLx_CAPABILITY_HEADER(RAS, 0x4)
55 CXLx_CAPABILITY_HEADER(LINK, 0x8)
56 CXLx_CAPABILITY_HEADER(HDM, 0xc)
57 CXLx_CAPABILITY_HEADER(EXTSEC, 0x10)
58 CXLx_CAPABILITY_HEADER(SNOOP, 0x14)
69 #define CXL_RAS_REGISTERS_OFFSET 0x80
70 #define CXL_RAS_REGISTERS_SIZE 0x58
72 #define CXL_RAS_UNC_ERR_CACHE_DATA_PARITY 0
88 REG32(CXL_RAS_UNC_ERR_MASK, CXL_RAS_REGISTERS_OFFSET + 0x4)
89 REG32(CXL_RAS_UNC_ERR_SEVERITY, CXL_RAS_REGISTERS_OFFSET + 0x8)
90 REG32(CXL_RAS_COR_ERR_STATUS, CXL_RAS_REGISTERS_OFFSET + 0xc)
91 #define CXL_RAS_COR_ERR_CACHE_DATA_ECC 0
98 REG32(CXL_RAS_COR_ERR_MASK, CXL_RAS_REGISTERS_OFFSET + 0x10)
99 REG32(CXL_RAS_ERR_CAP_CTRL, CXL_RAS_REGISTERS_OFFSET + 0x14)
100 FIELD(CXL_RAS_ERR_CAP_CTRL, FIRST_ERROR_POINTER, 0, 6)
103 REG32(CXL_RAS_ERR_HEADER0, CXL_RAS_REGISTERS_OFFSET + 0x18)
105 /* Offset 0x18 - 0x58 reserved for RAS logs */
110 #define CXL_SEC_REGISTERS_SIZE 0 /* We don't implement 1.1 downstream ports */
116 #define CXL_LINK_REGISTERS_SIZE 0x50
123 #define CXL_HDM_REGISTERS_SIZE (0x10 + 0x20 * HDM_DECODE_MAX)
126 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x10) \
129 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x14) \
131 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x18) \
133 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x1C) \
135 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x20) \
136 FIELD(CXL_HDM_DECODER##n##_CTRL, IG, 0, 4) \
149 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x24) \
151 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x28) \
153 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x24) \
155 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x28)
158 FIELD(CXL_HDM_DECODER_CAPABILITY, DECODER_COUNT, 0, 4)
170 FIELD(CXL_HDM_DECODER_GLOBAL_CONTROL, POISON_ON_ERR_EN, 0, 1)
176 HDM_DECODER_INIT(0);
195 #define CXL_IDE_REGISTERS_SIZE 0x24
201 #define CXL_SNOOP_REGISTERS_SIZE 0x8
204 CXL_SNOOP_REGISTERS_SIZE) >= 0x1000,
215 * 0x0000 - 0x0fff CXL.io registers
216 * 0x1000 - 0x1fff CXL.cache and CXL.mem
217 * 0x2000 - 0xdfff Implementation specific
218 * 0xe000 - 0xe3ff CXL ARB/MUX registers
219 * 0xe400 - 0xffff RSVD