41 #define SH_SERIAL_FLAG_TEND (1 << 0)
83     memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH);  in sh_serial_clear_fifo()
84     s->rx_cnt = 0;  in sh_serial_clear_fifo()
85     s->rx_head = 0;  in sh_serial_clear_fifo()
86     s->rx_tail = 0;  in sh_serial_clear_fifo()
98     case 0x00: /* SMR */  in sh_serial_write()
99         s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff);  in sh_serial_write()
101     case 0x04: /* BRR */  in sh_serial_write()
104     case 0x08: /* SCR */  in sh_serial_write()
105         /* TODO : For SH7751, SCIF mask should be 0xfb. */  in sh_serial_write()
106         s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff);  in sh_serial_write()
114             qemu_set_irq(s->rxi, 0);  in sh_serial_write()
117     case 0x0c: /* FTDR / TDR */  in sh_serial_write()
129 #if 0  in sh_serial_write()
130     case 0x14: /* FRDR / RDR */  in sh_serial_write()
131         ret = 0;  in sh_serial_write()
137         case 0x10: /* FSR */  in sh_serial_write()
150             if (!(val & (1 << 0))) {  in sh_serial_write()
154             if (!(val & (1 << 1)) || !(val & (1 << 0))) {  in sh_serial_write()
156                     qemu_set_irq(s->rxi, 0);  in sh_serial_write()
160         case 0x18: /* FCR */  in sh_serial_write()
163             case 0:  in sh_serial_write()
182         case 0x20: /* SPTR */  in sh_serial_write()
183             s->sptr = val & 0xf3;  in sh_serial_write()
185         case 0x24: /* LSR */  in sh_serial_write()
190 #if 0  in sh_serial_write()
191         case 0x0c:  in sh_serial_write()
194         case 0x10:  in sh_serial_write()
195             ret = 0;  in sh_serial_write()
198         case 0x1c:  in sh_serial_write()
199             s->sptr = val & 0x8f;  in sh_serial_write()
204                   "%s: unsupported write to 0x%02" HWADDR_PRIx "\n",  in sh_serial_write()
215 #if 0  in sh_serial_read()
217     case 0x00:  in sh_serial_read()
220     case 0x04:  in sh_serial_read()
223     case 0x08:  in sh_serial_read()
226     case 0x14:  in sh_serial_read()
227         ret = 0;  in sh_serial_read()
233         case 0x00: /* SMR */  in sh_serial_read()
236         case 0x08: /* SCR */  in sh_serial_read()
239         case 0x10: /* FSR */  in sh_serial_read()
240             ret = 0;  in sh_serial_read()
254                 ret |= (1 << 0);  in sh_serial_read()
262         case 0x14:  in sh_serial_read()
263             if (s->rx_cnt > 0) {  in sh_serial_read()
267                     s->rx_tail = 0;  in sh_serial_read()
274         case 0x18:  in sh_serial_read()
277         case 0x1c:  in sh_serial_read()
280         case 0x20:  in sh_serial_read()
283         case 0x24:  in sh_serial_read()
284             ret = 0;  in sh_serial_read()
289 #if 0  in sh_serial_read()
290         case 0x0c:  in sh_serial_read()
293         case 0x10:  in sh_serial_read()
294             ret = 0;  in sh_serial_read()
296         case 0x14:  in sh_serial_read()
297             ret = s->rx_fifo[0];  in sh_serial_read()
300         case 0x1c:  in sh_serial_read()
309                       "%s: unsupported read from 0x%02" HWADDR_PRIx "\n",  in sh_serial_read()
311         ret = 0;  in sh_serial_read()
319     return s->scr & (1 << 4) ? SH_RX_FIFO_LENGTH - s->rx_head : 0;  in sh_serial_can_receive()
351         for (i = 0; i < size; i++) {  in sh_serial_receive1()
354                 s->rx_head = 0;  in sh_serial_receive1()
369         s->rx_fifo[0] = buf[0];  in sh_serial_receive1()
394     s->smr = 0;  in sh_serial_reset()
395     s->brr = 0xff;  in sh_serial_reset()
397     s->sptr = 0;  in sh_serial_reset()
400         s->fcr = 0;  in sh_serial_reset()
402         s->dr = 0xff;  in sh_serial_reset()
414     memory_region_init_io(iomem, OBJECT(d), &sh_serial_ops, s, d->id, 0x28);  in sh_serial_realize()
442     DEFINE_PROP_UINT8("features", SHSerialState, feat, 0),