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/kvm-unit-tests/arm/
H A Dcstart64.S151 stp x11, x10, [sp, #-16]!
154 ldp x10, x11, [sp, #48]
155 \instr #0
157 ldr x10, [sp, #64]
158 cmp x10, xzr
160 stp x0, x1, [x10, #0]
161 stp x2, x3, [x10, #16]
162 stp x4, x5, [x10, #32]
163 stp x6, x7, [x10, #48]
164 stp x8, x9, [x10, #64]
[all …]
H A Dpmu.c24 #define PMU_PMCR_E (1 << 0)
33 #define PMU_PMCR_N_MASK 0x1f
35 #define PMU_PMCR_ID_MASK 0xff
37 #define PMU_PMCR_IMP_MASK 0xff
44 #define SW_INCR 0x0
45 #define INST_RETIRED 0x8
46 #define CPU_CYCLES 0x11
47 #define MEM_ACCESS 0x13
48 #define INST_PREC 0x1B
49 #define STALL_FRONTEND 0x23
[all …]
/kvm-unit-tests/lib/x86/
H A Dsetjmp64.S5 mov %rsp, 0x8(%rdi)
6 mov %rbp, 0x10(%rdi)
7 mov %rbx, 0x18(%rdi)
8 mov %r12, 0x20(%rdi)
9 mov %r13, 0x28(%rdi)
10 mov %r14, 0x30(%rdi)
11 mov %r15, 0x38(%rdi)
18 mov 0x38(%rdi), %r15
19 mov 0x30(%rdi), %r14
20 mov 0x28(%rdi), %r13
[all …]
H A Dapic.c28 asm volatile ("out %0, %1" : : "a"(data), "d"(port)); in outb()
33 apic_write(APIC_EOI, 0); in eoi()
76 asm volatile ("wrmsr" : : "a"(val), "d"(0), "c"(APIC_BASE_MSR + reg/16)); in x2apic_write()
112 return (apic_read(reg) & (1 << n)) != 0; in apic_read_bit()
130 asm volatile ("mov %%cr8, %0" : "=r"(tpr)); in apic_get_tpr()
140 asm volatile ("mov %0, %%cr8" : : "r"((unsigned long) tpr)); in apic_set_tpr()
150 asm ("cpuid" : "=a"(a), "=b"(b), "=c"(c), "=d"(d) : "0"(1)); in enable_x2apic()
159 return 0; in enable_x2apic()
182 xapic_write(APIC_SPIV, 0x1ff); in reset_apic()
188 return *(volatile u32 *)(g_ioapic + 0x10); in ioapic_read_reg()
[all …]
H A Ddesc.h6 * 0x00 NULL descriptor NULL descriptor
7 * 0x08 ring-0 code segment (32-bit) ring-0 code segment (64-bit)
8 * 0x10 ring-0 data segment (32-bit) ring-0 data segment (32/64-bit)
9 * 0x18 ring-0 code segment (P=0) ring-0 code segment (64-bit, P=0)
10 * 0x20 intr_alt_stack TSS ring-0 code segment (32-bit)
11 * 0x28 ring-0 code segment (16-bit) same
12 * 0x30 ring-0 data segment (16-bit) same
13 * 0x38 (0x3b) ring-3 code segment (32-bit) same
14 * 0x40 (0x43) ring-3 data segment (32-bit) ring-3 data segment (32/64-bit)
15 * 0x48 (0x4b) **unused** ring-3 code segment (64-bit)
[all …]
H A Ddesc.c11 idt_entry_t boot_idt[256] = {0};
21 { 0, 0, 0, .type_limit_flags = 0x0000}, /* 0x00 null */
22 {0xffff, 0, 0, .type_limit_flags = 0xcf9b}, /* flat 32-bit code segment */
23 {0xffff, 0, 0, .type_limit_flags = 0xcf93}, /* flat 32-bit data segment */
24 {0xffff, 0, 0, .type_limit_flags = 0xcf1b}, /* flat 32-bit code segment, not present */
25 { 0, 0, 0, .type_limit_flags = 0x0000}, /* TSS for task gates */
26 {0xffff, 0, 0, .type_limit_flags = 0x8f9b}, /* 16-bit code segment */
27 {0xffff, 0, 0, .type_limit_flags = 0x8f93}, /* 16-bit data segment */
28 {0xffff, 0, 0, .type_limit_flags = 0xcffb}, /* 32-bit code segment (user) */
29 {0xffff, 0, 0, .type_limit_flags = 0xcff3}, /* 32-bit data segment (user) */
[all …]
H A Dintel-iommu.h26 #define Q35_HOST_BRIDGE_IOMMU_ADDR 0xfed90000ULL
33 #define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */
34 #define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */
35 #define DMAR_CAP_REG_HI 0xc /* High 32-bit of DMAR_CAP_REG */
36 #define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */
37 #define DMAR_ECAP_REG_HI 0X14
38 #define DMAR_GCMD_REG 0x18 /* Global command */
39 #define DMAR_GSTS_REG 0x1c /* Global status */
40 #define DMAR_RTADDR_REG 0x20 /* Root entry table */
41 #define DMAR_RTADDR_REG_HI 0X24
[all …]
/kvm-unit-tests/s390x/
H A Dskey.c26 void *addr = (void *)0x10000 - 2 * PAGE_SIZE; in test_set_mb()
27 void *end = (void *)0x10000; in test_set_mb()
33 skey.val = 0x30; in test_set_mb()
46 skey1.val = 0x30; in test_chg()
47 set_storage_key(pagebuf, skey1.val, 0); in test_chg()
49 pagebuf[0] = 3; in test_chg()
58 skey.val = 0x30; in test_set()
60 set_storage_key(pagebuf, skey.val, 0); in test_set()
75 memset(pagebuf, 0, PAGE_SIZE * 2); in test_priv()
80 set_storage_key(pagebuf, 0x30, 0); in test_priv()
[all …]
H A Dsthyi.h16 CODE_UNSUPP = 0x04, /* with cc = 3 */
17 CODE_SUCCES = 0x00, /* with cc = 0 */
21 HDR_PERF_UNAV = 0x80,
22 HDR_STSI_UNAV = 0x40,
23 HDR_STACK_INCM = 0x20,
24 HDR_NOT_LPAR = 0x10,
28 MACH_CNT_VLD = 0x80,
29 MACH_ID_VLD = 0x40,
30 MACH_NAME_VLD = 0x20,
34 PART_MT_EN = 0x80,
[all …]
H A Dvector.c22 " vlm 0, 15, %[a]\n" in vlm_all()
43 " vl 0, %[v1]\n" in test_add()
45 " va 2, 0, 1, 4\n" in test_add()
66 memset(&prm, 0xff, sizeof(prm)); in test_ext1_nand()
69 " vl 0, %[v1]\n" in test_ext1_nand()
71 " .byte 0xe7, 0x20, 0x10, 0x00, 0x00, 0x6e\n" /* vnn */ in test_ext1_nand()
92 prm.c = 0; in test_bcd_add()
93 prm.a = prm.b = 0b001000011100; in test_bcd_add()
96 " vl 0, %[v1]\n" in test_bcd_add()
98 " .byte 0xe6, 0x20, 0x10, 0x01, 0x00, 0x71\n" /* vap */ in test_bcd_add()
[all …]
H A Ddiag10.c26 "diag %0,%1,0x10\n" in diag10()
35 report_prefix_push("0x0000/0x0000"); in test_prefix()
37 diag10(0, 0); in test_prefix()
42 report_prefix_push("0x1000/0x1000"); in test_prefix()
44 diag10(0x1000, 0x1000); in test_prefix()
48 report_prefix_push("0x0000/0x1000"); in test_prefix()
50 diag10(0, 0x1000); in test_prefix()
/kvm-unit-tests/lib/s390x/asm/
H A Dsie-arch.h8 #define CPUSTAT_STOPPED 0x80000000
9 #define CPUSTAT_WAIT 0x10000000
10 #define CPUSTAT_ECALL_PEND 0x08000000
11 #define CPUSTAT_STOP_INT 0x04000000
12 #define CPUSTAT_IO_INT 0x02000000
13 #define CPUSTAT_EXT_INT 0x01000000
14 #define CPUSTAT_RUNNING 0x00800000
15 #define CPUSTAT_RETAINED 0x00400000
16 #define CPUSTAT_TIMING_SUB 0x00020000
17 #define CPUSTAT_SIE_SUB 0x00010000
[all …]
/kvm-unit-tests/lib/powerpc/asm/
H A Dhcall.h9 #define SC1 0x44000022
10 #define SC1_REPLACEMENT 0x7c000268
12 #define H_SUCCESS 0
18 #define H_SET_SPRG0 0x24
19 #define H_SET_DABR 0x28
20 #define H_PAGE_INIT 0x2c
21 #define H_REGISTER_VPA 0xDC
22 #define H_CEDE 0xE0
23 #define H_GET_TERM_CHAR 0x54
24 #define H_PUT_TERM_CHAR 0x58
[all …]
/kvm-unit-tests/lib/arm64/asm/
H A Desr.h16 #define ESR_EL1_EC_UNKNOWN (0x00)
17 #define ESR_EL1_EC_WFI (0x01)
18 #define ESR_EL1_EC_CP15_32 (0x03)
19 #define ESR_EL1_EC_CP15_64 (0x04)
20 #define ESR_EL1_EC_CP14_MR (0x05)
21 #define ESR_EL1_EC_CP14_LS (0x06)
22 #define ESR_EL1_EC_FP_ASIMD (0x07)
23 #define ESR_EL1_EC_CP10_ID (0x08)
24 #define ESR_EL1_EC_CP14_64 (0x0C)
25 #define ESR_EL1_EC_ILL_ISS (0x0E)
[all …]
/kvm-unit-tests/x86/
H A Dcstart.S7 ipi_vector = 0x20
21 i = 0
23 .long 0x1e7 | (i << 22)
31 mb_magic = 0x1BADB002
32 mb_flags = 0x0
35 .long mb_magic, mb_flags, 0 - (mb_magic + mb_flags)
49 mov $0x10, %ax
81 bts $0, %eax
H A Dmsr.c27 #define addr_64 0x0000123456789abcULL
37 MSR_TEST(MSR_IA32_SYSENTER_CS, 0x1234, 0),
38 MSR_TEST(MSR_IA32_SYSENTER_ESP, addr_ul, 0),
39 MSR_TEST(MSR_IA32_SYSENTER_EIP, addr_ul, 0),
42 MSR_TEST(MSR_IA32_MISC_ENABLE, 0x400c50809, 0x1880),
43 MSR_TEST(MSR_IA32_CR_PAT, 0x07070707, 0),
44 MSR_TEST_ONLY64(MSR_FS_BASE, addr_64, 0),
45 MSR_TEST_ONLY64(MSR_GS_BASE, addr_64, 0),
46 MSR_TEST_ONLY64(MSR_KERNEL_GS_BASE, addr_64, 0),
47 MSR_TEST(MSR_EFER, EFER_SCE, 0),
[all …]
H A Dpku.c12 volatile int pf_count = 0;
31 write_pkru(0); in do_pf_tss()
55 pf_count = 0; in init_test()
59 write_pkru(0); in init_test()
60 set_cr0_wp(0); in init_test()
66 unsigned int pkey = 0x2; in main()
67 unsigned int pkru_ad = 0x10; in main()
68 unsigned int pkru_wd = 0x20; in main()
81 for (i = 0; i < USER_BASE; i += PAGE_SIZE) { in main()
100 report(pf_count == 0 && test == 21, in main()
[all …]
H A Dpks.c12 volatile int pf_count = 0;
29 printf("#PF handler, error code: 0x%lx\n", error_code); in do_pf_tss()
32 wrmsr(MSR_IA32_PKRS, 0); in do_pf_tss()
56 pf_count = 0; in init_test()
60 wrmsr(MSR_IA32_PKRS, 0); in init_test()
61 set_cr0_wp(0); in init_test()
67 unsigned int pkey = 0x2; in main()
68 unsigned int pkrs_ad = 0x10; in main()
69 unsigned int pkrs_wd = 0x20; in main()
83 for (i = 0; i < SUPER_BASE; i += PAGE_SIZE) { in main()
[all …]
H A Dapic.c11 #define MAX_TPR 0xf
39 report(version >= 0x10 && version <= 0x15, "apic existence"); in test_lapic_existence()
42 #define TSC_DEADLINE_TIMER_VECTOR 0xef
43 #define BROADCAST_VECTOR 0xcf
60 report(rdmsr(MSR_IA32_TSCDEADLINE) == 0, "tsc deadline timer clearing"); in __test_tsc_deadline_timer()
72 return 0; in enable_tsc_deadline_timer()
107 report(!test_write_apicbase_exception(apicbase | 0), in test_enable_x2apic()
132 memset((void *)APIC_DEFAULT_PHYS_BASE, 0xff, PAGE_SIZE); in verify_disabled_apic_mmio()
133 report(*lvr == ~0, "*0xfee00030: %x", *lvr); in verify_disabled_apic_mmio()
137 report(*tpr == ~0, "*0xfee00080: %x", *tpr); in verify_disabled_apic_mmio()
[all …]
/kvm-unit-tests/lib/libfdt/
H A Dfdt_ro.c21 return 0; in fdt_nodename_eq_()
23 if (memcmp(p, s, len) != 0) in fdt_nodename_eq_()
24 return 0; in fdt_nodename_eq_()
26 if (p[len] == '\0') in fdt_nodename_eq_()
31 return 0; in fdt_nodename_eq_()
51 if (totalsize < 0) in fdt_get_string()
61 if (stroffset < 0) in fdt_get_string()
72 if ((stroffset >= 0) || in fdt_get_string()
83 n = memchr(s, '\0', len); in fdt_get_string()
111 return p && (slen == len) && (memcmp(p, s, len) == 0); in fdt_string_eq_()
[all …]
/kvm-unit-tests/lib/linux/
H A Dpci_regs.h30 #define PCI_VENDOR_ID 0x00 /* 16 bits */
31 #define PCI_DEVICE_ID 0x02 /* 16 bits */
32 #define PCI_COMMAND 0x04 /* 16 bits */
33 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
34 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
35 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
36 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
37 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
38 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
39 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
[all …]
/kvm-unit-tests/riscv/
H A Dcstart.S27 REG_S zero, 0(\tmp1)
49 .dword 0x200000 // text offset
51 .dword 0 // flags
52 .word (0 << 16 | 2 << 0) // version
53 .word 0 // res1
54 .dword 0 // res2
55 .ascii "RISCV\0\0\0" // magic
57 .word 0 // res3
82 REG_S a5, 0(a4) // *addr = val
110 lw a0, 0(a0)
[all …]
/kvm-unit-tests/lib/arm/
H A Dio.c37 * the TX register at offset 0 from the base address, so there is no in uart0_init_fdt()
45 assert(ret >= 0 || ret == -FDT_ERR_NOTFOUND); in uart0_init_fdt()
49 for (i = 0; i < ARRAY_SIZE(compatible); i++) { in uart0_init_fdt()
51 assert(ret == 0 || ret == -FDT_ERR_NOTFOUND); in uart0_init_fdt()
53 if (ret == 0) in uart0_init_fdt()
63 is_pl011_uart = (i == 0); in uart0_init_fdt()
67 ret = dt_pbus_translate_node(ret, 0, &base); in uart0_init_fdt()
68 assert(ret == 0); in uart0_init_fdt()
125 if (!(readb(uart0_base + 6 * 4) & 0x10)) /* RX not empty? */ in __getchar()
128 if (readb(uart0_base + 5) & 0x01) /* RX data ready? */ in __getchar()
/kvm-unit-tests/lib/riscv/asm/
H A Dsbi.h5 #define SBI_SUCCESS 0
21 #define SBI_IMPL_BBL 0
36 #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
37 #define SBI_SPEC_VERSION_MINOR_MASK 0xffffff
45 SBI_EXT_BASE = 0x10,
46 SBI_EXT_TIME = 0x54494d45,
47 SBI_EXT_IPI = 0x735049,
48 SBI_EXT_HSM = 0x48534d,
49 SBI_EXT_SRST = 0x53525354,
50 SBI_EXT_DBCN = 0x4442434E,
[all …]
/kvm-unit-tests/riscv/efi/
H A Dcrt0-efi-riscv64.S35 .2byte 0
37 .2byte 0x5064 // riscv64
39 .4byte 0 // TimeDateStamp
40 .4byte 0 // PointerToSymbolTable
41 .4byte 0 // NumberOfSymbols
43 .2byte 0x206 // Characteristics.
48 .2byte 0x20b // PE32+ format
49 .byte 0x02 // MajorLinkerVersion
50 .byte 0x14 // MinorLinkerVersion
53 .4byte 0 // SizeOfUninitializedData
[all …]

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