Lines Matching +full:0 +full:x10
11 #define MAX_TPR 0xf
39 report(version >= 0x10 && version <= 0x15, "apic existence");
42 #define TSC_DEADLINE_TIMER_VECTOR 0xef
43 #define BROADCAST_VECTOR 0xcf
60 report(rdmsr(MSR_IA32_TSCDEADLINE) == 0, "tsc deadline timer clearing");
72 return 0;
107 report(!test_write_apicbase_exception(apicbase | 0),
132 memset((void *)APIC_DEFAULT_PHYS_BASE, 0xff, PAGE_SIZE);
133 report(*lvr == ~0, "*0xfee00030: %x", *lvr);
137 report(*tpr == ~0, "*0xfee00080: %x", *tpr);
159 report(*lvr == apic_version, "*0xfee00030: %x", *lvr);
160 report(*tpr == cr8, "*0xfee00080: %x", *tpr);
162 report(*tpr == (cr8 ^ MAX_TPR) << 4, "*0xfee00080: %x", *tpr);
174 #define ALTERNATE_APIC_BASE 0xfed40000
213 u32 initial_x2apic_id = cpuid(0xb).d;
232 report(initial_xapic_id == (apic_id() & 0xff), "sane x2apic id");
235 report(initial_xapic_id == (initial_x2apic_id & 0xff) &&
271 int vec = 0xf1;
275 id_map[0]);
279 } while (rdtsc() - start < 1000000000 && atomic_read(&ipi_count) == 0);
290 atomic_set(&ipi_count, 0);
304 atomic_set(&ipi_count, 0);
325 "post_sti: testb $0, %0 \n\t"
335 unsigned k = 0;
359 on_cpu_async(1, sti_loop, 0);
366 sti_loop_active = 0;
367 report(nmi_hlt_counter == 0, "nmi-after-sti");
390 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, id_map[0]);
393 | 0x44, id_map[0]);
403 apic_write(APIC_EOI, 0);
416 handle_irq(0x44, flush_nmi);
417 on_cpu_async(1, kick_me_nmi, 0);
418 for (i = 0; i < 100000; ++i) {
420 nmi_received = 0;
425 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, id_map[0]);
447 for (i = 0; i < 10; ++i)
448 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI, 0);
457 for (i = 0; i < 100000; ++i) {
458 nmi_received = 0;
460 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI, 0);
470 static volatile int lvtt_counter = 0;
481 static const uint32_t interval = 0x10000;
483 #define APIC_LVT_TIMER_VECTOR (0xee)
491 apic_write(APIC_TDCR, 0x0000000b);
530 atomic_set(&broadcast_counter, 0);
539 u32 broadcast_address = enable_x2apic() ? 0xffffffff : 0xff;
551 BROADCAST_VECTOR | APIC_DEST_ALLINC, 0);
566 /* Wait until the counter reach 0 or wrap-around */
567 while ( tmcct <= (initial_count / 2) && tmcct > 0 )
570 /* Wait specifically for wrap around to skip 0 TMCCR if we were asked to */
596 uint32_t tmict = 0x999999;
612 report(!apic_read(APIC_TMCCT), "TMCCT should have reached 0");
630 * Specifically wait for timer wrap around and skip 0.
632 * TMCCR reads return 0 while hrtimer is reset in an async callback
641 * TMCCT should be > 0 and count-down to 0
649 /* now tmcct == 0 and tmict != 0 */
659 unsigned long a0 = 0xFFFFFFFF, a1 = 0, a2 = 0xFFFFFFFF, a3 = 0x0;
688 atomic_set(&ipi_count, 0);
712 atomic_set(&ipi_count, 0);
714 return got == nr_ipis_expected ? 0 : 1;
721 if (dest == 0xff)
722 return 0;
724 set_ldr((void *)0);
726 (void *)((u32)logical_id | (cluster ? APIC_LDR_CLUSTER_FLAG : 0)));
735 if (dest == 0xff && cpu_count() > 2)
736 return 0;
738 set_ldr((void *)((u32)vcpu0_logical_id | (cluster ? APIC_LDR_CLUSTER_FLAG : 0)));
740 (void *)((u32)vcpu1_logical_id | (cluster ? APIC_LDR_CLUSTER_FLAG : 0)));
748 u8 vector = 0xf1;
763 f = 0;
764 for (i = 0; i < 8; i++) {
770 for (k = 0; k < 0xff; k++) {
786 f = 0;
787 for (c = 0; c < 0xf; c++) {
788 for (i = 0; i < 4; i++) {
790 for (k = 0; k < 0x10; k++) {
802 f = 0;
803 for (i = 0; i < 8 && !f; i++) {
804 for (j = 0; j < 8 && !f; j++) {
808 for (k = 0; k < 0x100 && !f; k++) {
824 f = 0;
825 for (c = 0; c < 0xf && !f; c++) {
826 for (i = 0; i < 4 && !f; i++) {
827 for (j = 0; j < 4 && !f; j++) {
831 for (k = 0; k < 0x10 && !f; k++) {
859 if (apic_id == 0xff)
874 u8 vector = 0xf1;
900 * Set both vCPU0 and vCPU1's APIC IDs to 0, then start the chain
901 * reaction of IPIs from APIC ID 0..255. Each vCPU will increment its
906 on_cpu(1, set_xapic_physical_id, (void *)0ul);
907 set_xapic_physical_id((void *)0ul);
909 f = 0;
910 for (i = 0; i < 0x100; i++)
963 for (i = 0; i < ARRAY_SIZE(tests); i++) {