| /qemu/scripts/ |
| H A D | meson-buildoptions.sh | 1 # This file is generated by meson-buildoptions.py, do not edit!
3 printf "%s\n" ' --audio-drv-list=CHOICES Set audio driver list [default] (choices: alsa/co'
6 printf "%s\n" ' --bindir=VALUE Executable directory [bin]'
7 printf "%s\n" ' --block-drv-ro-whitelist=VALUE'
8 printf "%s\n" ' set block driver read-only whitelist (by default'
9 printf "%s\n" ' affects only QEMU, not tools like qemu-img)'
10 printf "%s\n" ' --block-drv-rw-whitelist=VALUE'
11 printf "%s\n" ' set block driver read-write whitelist (by default'
12 printf "%s\n" ' affects only QEMU, not tools like qemu-img)'
13 printf "%s\n" ' --datadir=VALUE Data file directory [share]'
[all …]
|
| H A D | meson-buildoptions.py | 28 # Options with nonstandard names (e.g. --with/--without) or OS-dependent
40 "coroutine_backend": "with-coroutine",
41 "debug": "debug-info",
42 "malloc": "enable-malloc",
43 "pkgversion": "with-pkgversion",
45 "qemu_suffix": "with-suffix",
46 "trace_backends": "enable-trace-backends",
47 "trace_file": "with-trace-file",
58 # via -D, because it's a mix of CFLAGS and --extra-cflags); for specific
59 # cases "../configure -D" can be used as an escape hatch.
[all …]
|
| /qemu/scripts/coverity-scan/ |
| H A D | run-coverity-scan | 1 #!/bin/sh -e
8 # See the COPYING file in the top-level directory.
10 # Copyright (c) 2017-2020 Linaro Limited
14 # run the (closed-source) coverity build tools, so don't
18 # tree, and that tree is a fresh clean one, because we do an in-tree
21 # regular expressions it uses; an out-of-tree build won't work for this.)
31 # --check-upload-only : return success if upload is possible
32 # --dry-run : run the tools, but don't actually do the upload
33 # --docker : create and work inside a container
34 # --docker-engine : specify the container engine to use (docker/podman/auto);
[all …]
|
| /qemu/tests/docker/ |
| H A D | test-mingw | 1 #!/bin/bash -e
12 # the top-level directory.
16 requires_binary x86_64-w64-mingw32-gcc i686-w64-mingw32-gcc
20 TARGET_LIST=${TARGET_LIST:-$DEF_TARGET_LIST} \
22 --enable-trace-backends=simple \
23 --enable-gnutls \
24 --enable-nettle \
25 --enable-curl \
26 --enable-vnc \
27 --enable-bzip2 \
[all …]
|
| /qemu/include/hw/misc/ |
| H A D | aspeed_scu.h | 9 * the COPYING file in the top-level directory.
19 #define TYPE_ASPEED_2400_SCU TYPE_ASPEED_SCU "-ast2400"
20 #define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU "-ast2500"
21 #define TYPE_ASPEED_2600_SCU TYPE_ASPEED_SCU "-ast2600"
22 #define TYPE_ASPEED_2700_SCU TYPE_ASPEED_SCU "-ast2700"
23 #define TYPE_ASPEED_2700_SCUIO TYPE_ASPEED_SCU "io" "-ast2700"
24 #define TYPE_ASPEED_1030_SCU TYPE_ASPEED_SCU "-ast1030"
86 * arch/arm/mach-aspeed/include/mach/regs-scu.h
88 * Copyright (C) 2012-2020 ASPEED Technology Inc.
101 * 31 Enable Video Engine clock dynamic slow down
[all …]
|
| /qemu/.gitlab-ci.d/ |
| H A D | buildtest.yml | 2 - local: '/.gitlab-ci.d/buildtest-template.yml'
4 build-system-alpine:
6 - .native_build_job_template
7 - .native_build_artifact_template
9 - job: amd64-alpine-container
12 TARGETS: avr-softmmu loongarch64-softmmu mips64-softmmu mipsel-softmmu
13 MAKE_CHECK_ARGS: check-build
14 CONFIGURE_ARGS: --enable-docs --enable-trace-backends=log,simple,syslog
16 check-system-alpine:
19 - job: build-system-alpine
[all …]
|
| /qemu/hw/char/ |
| H A D | stm32l4x5_usart.c | 4 * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5 * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
7 * SPDX-License-Identifier: GPL-2.0-or-later
10 * See the COPYING file in the top-level directory.
15 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
22 #include "chardev/char-fe.h"
23 #include "chardev/char-serial.h"
28 #include "hw/qdev-clock.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/qdev-properties-system.h"
[all …]
|
| /qemu/docs/system/i386/ |
| H A D | kvm-pv.rst | 5 -----------
11 -----
17 - ``kvmclock``
18 - ``kvm-nopiodelay``
19 - ``kvm-asyncpf``
20 - ``kvm-steal-time``
21 - ``kvm-pv-eoi``
22 - ``kvmclock-stable-bit``
24 ``kvm-msi-ext-dest-id`` feature is enabled by default in x2apic mode with split
25 irqchip (e.g. "-machine ...,kernel-irqchip=split -cpu ...,x2apic").
[all …]
|
| /qemu/hw/intc/ |
| H A D | aspeed_vic.c | 9 * the COPYING file in the top-level directory.
24 * Additionally, the "Interrupt Enable", "Edge Status" and "Software Interrupt"
25 * fields have separate "enable"/"status" and "clear" registers, where set bits
27 * read-modify-write sequence).
47 uint64_t new = (s->raw & s->enable); in aspeed_vic_update()
50 flags = new & s->select; in aspeed_vic_update()
52 qemu_set_irq(s->fiq, !!flags); in aspeed_vic_update()
54 flags = new & ~s->select; in aspeed_vic_update()
56 qemu_set_irq(s->irq, !!flags); in aspeed_vic_update()
74 if (s->sense & irq_mask) { in aspeed_vic_set_irq()
[all …]
|
| /qemu/docs/system/arm/ |
| H A D | virt.rst | 1 .. _arm-virt:
10 idiosyncrasies and limitations of a particular bit of real-world
18 ``virt-5.0`` machine type will behave like the ``virt`` machine from
19 the QEMU 5.0 release, and migration should work between ``virt-5.0``
20 of the 5.0 release and ``virt-5.0`` of the 5.1 release. Migration
22 the non-versioned ``virt`` machine type.
24 VM migration is not guaranteed when using ``-cpu max``, as features
33 - PCI/PCIe devices
34 - Flash memory
35 - Either one or two PL011 UARTs for the NonSecure World
[all …]
|
| H A D | cpu-features.rst | 10 Cortex-A15 and the Cortex-A57, which respectively implement Arm
11 architecture reference manuals ARMv7-A and ARMv8-A, may both optionally
12 implement PMUs. For example, if a user wants to use a Cortex-A15 without
13 a PMU, then the ``-cpu`` parameter should contain ``pmu=off`` on the QEMU
14 command line, i.e. ``-cpu cortex-a15,pmu=off``.
18 that implement the ARMv8-A architecture reference manual may optionally
20 ``aarch64`` CPU property. A CPU type such as the Cortex-A15, which does
21 not implement ARMv8-A, will not have the ``aarch64`` CPU property.
30 prefixed with "kvm-" and are described in "KVM VCPU Features".
36 CPU type is possible with the ``query-cpu-model-expansion`` QMP command.
[all …]
|
| /qemu/include/standard-headers/linux/ |
| H A D | pci_regs.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
5 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
25 * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
26 * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of
41 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
42 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
43 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
44 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
46 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
47 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
[all …]
|
| /qemu/include/hw/usb/ |
| H A D | ehci-regs.h | 4 /* Capability Registers Base Address - section 2.2 */
5 #define CAPLENGTH 0x0000 /* 1-byte, 0x0001 reserved */
6 #define HCIVERSION 0x0002 /* 2-bytes, i/f version # */
7 #define HCSPARAMS 0x0004 /* 4-bytes, structural params */
8 #define HCCPARAMS 0x0008 /* 4-bytes, capability params */
18 #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable
19 #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable
23 #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable
41 * Interrupt enable bits correspond to the interrupt active bits in USBSTS
56 * Bits that are reserved or are read-only are masked out of values
[all …]
|
| /qemu/linux-user/arm/nwfpe/ |
| H A D | fpsr.h | 3 (c) Rebel.com, 1998-1999
29 EXCEPTION TRAP ENABLE BYTE
37 ------------
48 /* EXCEPTION TRAP ENABLE BYTE
49 ----------------------------- */
53 #define BIT_IXE 0x00100000 /* inexact exception enable */
54 #define BIT_UFE 0x00080000 /* underflow exception enable */
55 #define BIT_OFE 0x00040000 /* overflow exception enable */
56 #define BIT_DZE 0x00020000 /* divide by zero exception enable */
57 #define BIT_IOE 0x00010000 /* invalid operation exception enable */
[all …]
|
| /qemu/scripts/kvm/ |
| H A D | kvm_flightrecorder | 3 # KVM Flight Recorder - ring buffer tracing script
9 # This script provides a command-line interface to kvm ftrace and is designed
10 # to be used as a flight recorder that is always running. To start in-memory
13 # sudo kvm_flightrecorder start 8192 # 8 MB per-cpu ring buffers
15 # The per-cpu ring buffer size can be given in KB as an optional argument to
33 # fixed-size in-memory trace.
46 def enable_event(subsystem, event, enable): argument
47 write_file(trace_path('events', subsystem, event, 'enable'), '1' if enable else '0')
49 def enable_subsystem(subsystem, enable): argument
50 write_file(trace_path('events', subsystem, 'enable'), '1' if enable else '0')
[all …]
|
| H A D | vmxcap | 5 # Copyright 2009-2010 Red Hat, Inc.
11 # the COPYING file in the top-level directory.
74 print(' %-40s %s' % (self.bits[bit], s))
76 # All 64 bits in the tertiary controls MSR are allowed-1
105 v = (value >> lo) & ((1 << (hi - lo + 1)) - 1)
106 print(' %-40s %s' % (self.bits[bits], fmt(v)))
115 49: 'Dual-monitor support',
125 name = 'pin-based controls',
130 6: 'Activate VMX-preemption timer',
138 name = 'primary processor-based controls',
[all …]
|
| /qemu/hw/net/ |
| H A D | e1000x_regs.h | 4 Copyright(c) 1999 - 2006 Intel Corporation.
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
115 * RW - register is both readable and writable
116 * RO - register is read only
117 * WO - register is write only
118 * R/clr - register is read only and is cleared when read
119 * A - register array
121 #define E1000_CTRL 0x00000 /* Device Control - RW */
122 #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
[all …]
|
| H A D | igb_regs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
51 /* Receive Descriptor - Advanced */
94 /* Enable flexible speed on link-up */
107 #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */
170 #define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
171 #define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
179 /* IPSec Encrypt Enable for ESP */
186 #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */
189 #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */
196 #define E1000_DCA_RXCTRL_DESC_DCA_EN BIT(5) /* DCA Rx Desc enable */
[all …]
|
| /qemu/qapi/ |
| H A D | control.json | 1 # -*- Mode: Python -*-
12 # Enable QMP capabilities.
14 # @enable: An optional list of QMPCapability values to enable. The
15 # client must not enable any capability that is not mentioned in
19 # .. qmp-example::
21 # -> { "execute": "qmp_capabilities",
22 # "arguments": { "enable": [ "oob" ] } }
23 # <- { "return": {} }
28 # :doc:`/interop/qmp-spec`)
30 # .. note:: The QMP client needs to explicitly enable QMP
[all …]
|
| /qemu/docs/devel/ |
| H A D | tracing.rst | 16 Enable tracing of ``memory_region_ops_read`` and ``memory_region_ops_write``
19 $ qemu --trace "memory_region_ops_*" ...
25 ``./configure --enable-trace-backends=BACKENDS`` was not explicitly specified.
27 Multiple patterns can be specified by repeating the ``--trace`` option::
29 $ qemu --trace "kvm_*" --trace "virtio_*" ...
32 file to avoid long command-line options::
36 $ qemu --trace events=/tmp/events ...
41 Sub-directory setup
42 -------------------
45 "trace-events" file. All directories which contain "trace-events" files must be
[all …]
|
| /qemu/include/hw/xen/interface/hvm/ |
| H A D | params.h | 1 /* SPDX-License-Identifier: MIT */
34 * How should CPU0 event-channel notifications be delivered?
36 * If val == 0 then CPU0 event-channel notifications are not delivered.
62 * val[15:8] is interrupt flag of the PPI used by event-channel:
65 * val[7:0] is a PPI number used by event-channel.
74 * These are not used by Xen. They are here for convenience of HVM-guest
89 …* (See http://download.microsoft.com/download/A/B/4/AB43A34E-BDD0-4FA6-BDEF-79EEF16E880B/Hyperviso…
99 * - Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL)
100 * - APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR)
101 * - Virtual Processor index MSR (HV_X64_MSR_VP_INDEX)
[all …]
|
| /qemu/net/ |
| H A D | netmap.c | 4 * Copyright (c) 2012-2013 Luigi Rizzo
36 #include "qemu/error-report.h"
40 #include "qemu/main-loop.h"
51 int vnet_hdr_len; /* Current virtio-net header length. */
67 for (; l > 0; l -= 64) { in pkt_copy()
92 nmd = nm_open(nm_opts->ifname, &req, NETMAP_NO_TX_POLL, in netmap_open()
96 nm_opts->ifname); in netmap_open()
106 /* Set the event-loop handlers for the netmap backend. */
109 qemu_set_fd_handler(s->nmd->fd, in netmap_update_fd_handler()
110 s->read_poll ? netmap_send : NULL, in netmap_update_fd_handler()
[all …]
|
| /qemu/rust/hw/char/pl011/src/ |
| H A D | registers.rs | 3 // SPDX-License-Identifier: GPL-2.0-or-later
40 /// `IrDA` Low-Power Counter Register
94 /// read for RX. It is a 12-bit register, where bits 7..0 are the
107 // bilge is not very const-friendly, unfortunately
142 fn default() -> Self { in default()
151 /// This has the usual inbound RS232 modem-control signals, plus flags
185 fn default() -> Self { in default()
201 /// PEN: Parity enable
207 /// FEN: Enable FIFOs
217 /// 31:8 - Reserved, do not modify, read as zero.
[all …]
|
| /qemu/include/hw/char/ |
| H A D | imx_serial.h | 7 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
22 #include "chardev/char-fe.h"
67 #define UCR1_TRDYEN (1<<13) /* Tx Ready Interrupt Enable */
68 #define UCR1_RRDYEN (1<<9) /* Rx Ready Interrupt Enable */
69 #define UCR1_TXMPTYEN (1<<6) /* Tx Empty Interrupt Enable */
70 #define UCR1_UARTEN (1<<0) /* UART Enable */
72 #define UCR2_ATEN (1<<3) /* Ageing Timer Enable */
73 #define UCR2_TXEN (1<<2) /* Transmitter enable */
74 #define UCR2_RXEN (1<<1) /* Receiver enable */
77 #define UCR4_DREN BIT(0) /* Receive Data Ready interrupt enable */
[all …]
|
| /qemu/docs/devel/migration/ |
| H A D | qpl-compression.rst | 4 The Intel Query Processing Library (Intel ``QPL``) is an open-source library to
8 The ``QPL`` compression relies on Intel In-Memory Analytics Accelerator(``IAA``)
21 +----------------+ +------------------+
22 | MultiFD Thread | |accel-config tool |
23 +-------+--------+ +--------+---------+
27 +-------+--------+ | Setup IAA
29 +-------+---+----+ |
31 | +-------------+-------+
33 | Devices +-----+-----+
35 | +-----+-----+
[all …]
|