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1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
5 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
25 * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
26 * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of
41 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
42 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
43 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
44 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
46 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
47 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
48 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
49 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */
50 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
59 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
83 #define PCI_HEADER_TYPE_MFD 0x80 /* Multi-Function Device (possible) */
124 /* 0x35-0x3b are reserved */
130 /* Header type 1 (PCI-to-PCI bridges) */
158 /* 0x35-0x3b is reserved */
160 /* 0x3c-0x3d are same as for htype 0 */
162 #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
164 #define PCI_BRIDGE_CTL_ISA 0x04 /* Enable ISA mode */
191 /* 0x3c-0x3d are same as for htype 0 */
199 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
200 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
205 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
206 /* 0x48-0x7f reserved */
217 #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
219 #define PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */
222 #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
224 #define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
227 #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
256 #define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */
257 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
263 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
272 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
274 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
283 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
295 #define PCI_VPD_DATA 4 /* 32-bits of data returned here */
311 #define PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */
312 #define PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking capable */
316 #define PCI_MSI_DATA_32 0x08 /* 16 bits of data for 32-bit devices */
317 #define PCI_MSI_MASK_32 0x0c /* Mask bits register for 32-bit devices */
318 #define PCI_MSI_PENDING_32 0x10 /* Pending intrs for 32-bit devices */
319 #define PCI_MSI_DATA_64 0x0c /* 16 bits of data for 64-bit devices */
320 #define PCI_MSI_MASK_64 0x10 /* Mask bits register for 64-bit devices */
321 #define PCI_MSI_PENDING_64 0x14 /* Pending intrs for 64-bit devices */
323 /* MSI-X registers (in MSI-X capability) */
327 #define PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSI-X enable */
337 /* MSI-X Table entry format (in memory mapped by a BAR) */
354 #define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */
355 #define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */
383 /* 0-5 map to BARs 0-5 respectively */
389 /* 9-14 map to VF BARs 0-5 respectively */
392 #define PCI_EA_BEI_RESERVED 15 /* Reserved - Treat like ENI */
395 #define PCI_EA_P_MEM 0x00 /* Non-Prefetch Memory */
399 #define PCI_EA_P_VF_MEM 0x04 /* VF Non-Prefetch Memory */
400 #define PCI_EA_P_BRIDGE_MEM 0x05 /* Bridge Non-Prefetch Memory */
403 /* 0x08-0xfc reserved */
408 #define PCI_EA_ENABLE 0x80000000 /* Enable for this entry */
412 #define PCI_EA_IS_64 0x00000002 /* 64-bit field flag */
415 /* PCI-X registers (Type 0 (non-bridge) devices) */
418 #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
419 #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
436 #define PCI_X_STATUS 4 /* PCI-X capabilities */
439 #define PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */
455 /* PCI-X registers (Type 1 (bridge) devices) */
461 #define PCI_X_SSTATUS_VERS 0x3000 /* PCI-X Capability Version */
483 #define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCIe to PCI/PCI-X Bridge */
484 #define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */
499 #define PCI_EXP_DEVCAP_RBER 0x00008000 /* Role-Based Error Reporting */
505 #define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
506 #define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
508 #define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
516 #define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
517 #define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
518 #define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
519 #define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
530 #define PCI_EXP_DEVSTA_NFED 0x0002 /* Non-Fatal Error Detected */
557 #define PCI_EXP_LNKCTL_ASPM_L0S 0x0001 /* L0s Enable */
558 #define PCI_EXP_LNKCTL_ASPM_L1 0x0002 /* L1 Enable */
564 #define PCI_EXP_LNKCTL_CLKREQ_EN 0x0100 /* Enable clkreq */
566 #define PCI_EXP_LNKCTL_LBMIE 0x0400 /* Link Bandwidth Management Interrupt Enable */
567 #define PCI_EXP_LNKCTL_LABIE 0x0800 /* Link Autonomous Bandwidth Interrupt Enable */
594 #define PCI_EXP_SLTCAP_HPS 0x00000020 /* Hot-Plug Surprise */
595 #define PCI_EXP_SLTCAP_HPC 0x00000040 /* Hot-Plug Capable */
602 #define PCI_EXP_SLTCTL_ABPE 0x0001 /* Attention Button Pressed Enable */
603 #define PCI_EXP_SLTCTL_PFDE 0x0002 /* Power Fault Detected Enable */
604 #define PCI_EXP_SLTCTL_MRLSCE 0x0004 /* MRL Sensor Changed Enable */
605 #define PCI_EXP_SLTCTL_PDCE 0x0008 /* Presence Detect Changed Enable */
606 #define PCI_EXP_SLTCTL_CCIE 0x0010 /* Command Completed Interrupt Enable */
607 #define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */
621 #define PCI_EXP_SLTCTL_DLLSCE 0x1000 /* Data Link Layer State Changed Enable */
623 #define PCI_EXP_SLTCTL_IBPD_DISABLE 0x4000 /* In-band PD disable */
636 #define PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error */
638 #define PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */
639 #define PCI_EXP_RTCTL_RRS_SVE 0x0010 /* Config RRS Software Visibility Enable */
658 #define PCI_EXP_DEVCAP2_ARI 0x00000020 /* Alternative Routing-ID */
667 #define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */
668 #define PCI_EXP_DEVCAP2_EE_PREFIX 0x00200000 /* End-End TLP Prefix */
669 #define PCI_EXP_DEVCAP2_EE_PREFIX_MAX 0x00c00000 /* Max End-End TLP Prefixes */
673 #define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */
678 #define PCI_EXP_DEVCTL2_LTR_EN 0x0400 /* Enable LTR mechanism */
679 #define PCI_EXP_DEVCTL2_OBFF_MSGA_EN 0x2000 /* Enable OBFF Message type A */
680 #define PCI_EXP_DEVCTL2_OBFF_MSGB_EN 0x4000 /* Enable OBFF Message type B */
708 #define PCI_EXP_SLTCAP2_IBPD 0x00000001 /* In-band PD Disable Supported */
712 /* Extended Capabilities (PCI-X 2.0 and Express) */
724 #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */
727 #define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */
728 #define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */
747 #define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */
787 #define PCI_ERR_COR_ADV_NFAT 0x00002000 /* Advisory Non-Fatal */
795 #define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */
797 #define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
803 #define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 /* Correctable Err Reporting Enable */
804 #define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 /* Non-Fatal Err Reporting Enable */
805 #define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 /* Fatal Err Reporting Enable */
812 #define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */
870 /* Vendor-Specific (VSEC, PCI_EXT_CAP_ID_VNDR) */
871 #define PCI_VNDR_HEADER 4 /* Vendor-Specific Header */
896 #define HT_MSI_FLAGS_ENABLE 0x1 /* Mapping enable */
910 /* Alternative Routing-ID Interpretation */
916 #define PCI_ARI_CTRL_MFVC 0x0001 /* MFVC Function Groups Enable */
917 #define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */
927 #define PCI_ATS_CTRL_ENABLE 0x8000 /* ATS Enable */
934 #define PCI_PRI_CTRL_ENABLE 0x0001 /* Enable */
951 #define PCI_PASID_CTRL_ENABLE 0x0001 /* Enable bit */
952 #define PCI_PASID_CTRL_EXEC 0x0002 /* Exec permissions Enable */
953 #define PCI_PASID_CTRL_PRIV 0x0004 /* Privilege Mode Enable */
957 #define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
960 #define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */
961 #define PCI_SRIOV_CTRL_VFE 0x0001 /* VF Enable */
962 #define PCI_SRIOV_CTRL_VFM 0x0002 /* VF Migration Enable */
963 #define PCI_SRIOV_CTRL_INTR 0x0004 /* VF Migration Interrupt Enable */
964 #define PCI_SRIOV_CTRL_MSE 0x0008 /* VF Memory Space Enable */
966 #define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */
993 #define PCI_LTR_NOSNOOP_VALUE 0x03ff0000 /* Max No-Snoop Latency Value */
1012 #define PCI_SATA_REGS_MASK 0xF /* location - BAR#/inline */
1029 #define PCI_DPA_CAP_SUBSTATE_MASK 0x1F /* # substates - 1 */
1046 #define PCI_TPH_LOC_MSIX 0x00000400 /* In MSI-X */
1056 #define PCI_TPH_CTRL_REQ_EN_MASK 0x00000300 /* TPH Requester Enable */
1072 #define PCI_EXP_DPC_CTL_EN_FATAL 0x0001 /* Enable trigger on ERR_FATAL message */
1073 #define PCI_EXP_DPC_CTL_EN_NONFATAL 0x0002 /* Enable trigger on ERR_NONFATAL message */
1074 #define PCI_EXP_DPC_CTL_INT_EN 0x0008 /* DPC Interrupt Enable */
1108 #define PCI_PTM_CTRL_ENABLE 0x00000001 /* PTM enable */
1113 #define PCI_L1SS_CAP_PCIPM_L1_2 0x00000001 /* PCI-PM L1.2 Supported */
1114 #define PCI_L1SS_CAP_PCIPM_L1_1 0x00000002 /* PCI-PM L1.1 Supported */
1122 #define PCI_L1SS_CTL1_PCIPM_L1_2 0x00000001 /* PCI-PM L1.2 Enable */
1123 #define PCI_L1SS_CTL1_PCIPM_L1_1 0x00000002 /* PCI-PM L1.1 Enable */
1124 #define PCI_L1SS_CTL1_ASPM_L1_2 0x00000004 /* ASPM L1.2 Enable */
1125 #define PCI_L1SS_CTL1_ASPM_L1_1 0x00000008 /* ASPM L1.1 Enable */
1135 /* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */
1136 #define PCI_DVSEC_HEADER1 0x4 /* Designated Vendor-Specific Header1 */
1140 #define PCI_DVSEC_HEADER2 0x8 /* Designated Vendor-Specific Header2 */
1145 #define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */
1158 #define PCI_NPEM_CTRL_ENABLE 0x00000001 /* NPEM Enable */
1193 #define PCI_DOE_CTRL_INT_EN 0x00000002 /* DOE Interrupt Enable */
1204 /* DOE Data Object - note not actually registers */