Lines Matching +full:- +full:- +full:enable +full:-

4 /* Capability Registers Base Address - section 2.2 */
5 #define CAPLENGTH        0x0000  /* 1-byte, 0x0001 reserved */
6 #define HCIVERSION       0x0002  /* 2-bytes, i/f version # */
7 #define HCSPARAMS        0x0004  /* 4-bytes, structural params */
8 #define HCCPARAMS        0x0008  /* 4-bytes, capability params */
18 #define USBCMD_PSE       (1 << 4)      // Periodic Schedule Enable
19 #define USBCMD_ASE       (1 << 5)      // Asynch Schedule Enable
23 #define USBCMD_ASPME     (1 << 11)     // Async Sched Park Mode Enable
41  *  Interrupt enable bits correspond to the interrupt active bits in USBSTS
56  * Bits that are reserved or are read-only are masked out of values
61 #define PORTSC_WKOC_E        (1 << 22)    // Wake on Over Current Enable
62 #define PORTSC_WKDS_E        (1 << 21)    // Wake on Disconnect Enable
63 #define PORTSC_WKCN_E        (1 << 20)    // Wake on Connect Enable
77 #define PORTSC_PEDC          (1 << 3)     // Port Enable/Disable Change
78 #define PORTSC_PED           (1 << 2)     // Port Enable/Disable