100406dffSbellard /* 200406dffSbellard NetWinder Floating Point Emulator 300406dffSbellard (c) Rebel.com, 1998-1999 400406dffSbellard 500406dffSbellard Direct questions, comments to Scott Bambrough <scottb@netwinder.org> 600406dffSbellard 700406dffSbellard This program is free software; you can redistribute it and/or modify 800406dffSbellard it under the terms of the GNU General Public License as published by 900406dffSbellard the Free Software Foundation; either version 2 of the License, or 1000406dffSbellard (at your option) any later version. 1100406dffSbellard 1200406dffSbellard This program is distributed in the hope that it will be useful, 1300406dffSbellard but WITHOUT ANY WARRANTY; without even the implied warranty of 1400406dffSbellard MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1500406dffSbellard GNU General Public License for more details. 1600406dffSbellard 1700406dffSbellard You should have received a copy of the GNU General Public License 1870539e18SBlue Swirl along with this program; if not, see <http://www.gnu.org/licenses/>. 1900406dffSbellard */ 2000406dffSbellard 21*2a6a4076SMarkus Armbruster #ifndef FPSR_H 22*2a6a4076SMarkus Armbruster #define FPSR_H 2300406dffSbellard 2400406dffSbellard /* 2500406dffSbellard The FPSR is a 32 bit register consisting of 4 parts, each exactly 2600406dffSbellard one byte. 2700406dffSbellard 2800406dffSbellard SYSTEM ID 2900406dffSbellard EXCEPTION TRAP ENABLE BYTE 3000406dffSbellard SYSTEM CONTROL BYTE 3100406dffSbellard CUMULATIVE EXCEPTION FLAGS BYTE 3200406dffSbellard 3300406dffSbellard The FPCR is a 32 bit register consisting of bit flags. 3400406dffSbellard */ 3500406dffSbellard 3600406dffSbellard /* SYSTEM ID 3700406dffSbellard ------------ 3800406dffSbellard Note: the system id byte is read only */ 3900406dffSbellard 4000406dffSbellard typedef unsigned int FPSR; /* type for floating point status register */ 4100406dffSbellard typedef unsigned int FPCR; /* type for floating point control register */ 4200406dffSbellard 4300406dffSbellard #define MASK_SYSID 0xff000000 4400406dffSbellard #define BIT_HARDWARE 0x80000000 4500406dffSbellard #define FP_EMULATOR 0x01000000 /* System ID for emulator */ 4600406dffSbellard #define FP_ACCELERATOR 0x81000000 /* System ID for FPA11 */ 4700406dffSbellard 4800406dffSbellard /* EXCEPTION TRAP ENABLE BYTE 4900406dffSbellard ----------------------------- */ 5000406dffSbellard 5100406dffSbellard #define MASK_TRAP_ENABLE 0x00ff0000 5200406dffSbellard #define MASK_TRAP_ENABLE_STRICT 0x001f0000 5300406dffSbellard #define BIT_IXE 0x00100000 /* inexact exception enable */ 5400406dffSbellard #define BIT_UFE 0x00080000 /* underflow exception enable */ 5500406dffSbellard #define BIT_OFE 0x00040000 /* overflow exception enable */ 5600406dffSbellard #define BIT_DZE 0x00020000 /* divide by zero exception enable */ 5700406dffSbellard #define BIT_IOE 0x00010000 /* invalid operation exception enable */ 5800406dffSbellard 5900406dffSbellard /* SYSTEM CONTROL BYTE 6000406dffSbellard ---------------------- */ 6100406dffSbellard 6200406dffSbellard #define MASK_SYSTEM_CONTROL 0x0000ff00 6300406dffSbellard #define MASK_TRAP_STRICT 0x00001f00 6400406dffSbellard 6500406dffSbellard #define BIT_AC 0x00001000 /* use alternative C-flag definition 6600406dffSbellard for compares */ 6700406dffSbellard #define BIT_EP 0x00000800 /* use expanded packed decimal format */ 6800406dffSbellard #define BIT_SO 0x00000400 /* select synchronous operation of FPA */ 6900406dffSbellard #define BIT_NE 0x00000200 /* NaN exception bit */ 7000406dffSbellard #define BIT_ND 0x00000100 /* no denormalized numbers bit */ 7100406dffSbellard 7200406dffSbellard /* CUMULATIVE EXCEPTION FLAGS BYTE 7300406dffSbellard ---------------------------------- */ 7400406dffSbellard 7500406dffSbellard #define MASK_EXCEPTION_FLAGS 0x000000ff 7600406dffSbellard #define MASK_EXCEPTION_FLAGS_STRICT 0x0000001f 7700406dffSbellard 7800406dffSbellard #define BIT_IXC 0x00000010 /* inexact exception flag */ 7900406dffSbellard #define BIT_UFC 0x00000008 /* underflow exception flag */ 8000406dffSbellard #define BIT_OFC 0x00000004 /* overfloat exception flag */ 8100406dffSbellard #define BIT_DZC 0x00000002 /* divide by zero exception flag */ 8200406dffSbellard #define BIT_IOC 0x00000001 /* invalid operation exception flag */ 8300406dffSbellard 8400406dffSbellard /* Floating Point Control Register 8500406dffSbellard ----------------------------------*/ 8600406dffSbellard 8700406dffSbellard #define BIT_RU 0x80000000 /* rounded up bit */ 8800406dffSbellard #define BIT_IE 0x10000000 /* inexact bit */ 8900406dffSbellard #define BIT_MO 0x08000000 /* mantissa overflow bit */ 9000406dffSbellard #define BIT_EO 0x04000000 /* exponent overflow bit */ 9100406dffSbellard #define BIT_SB 0x00000800 /* store bounce */ 9200406dffSbellard #define BIT_AB 0x00000400 /* arithmetic bounce */ 9300406dffSbellard #define BIT_RE 0x00000200 /* rounding exception */ 9400406dffSbellard #define BIT_DA 0x00000100 /* disable FPA */ 9500406dffSbellard 9600406dffSbellard #define MASK_OP 0x00f08010 /* AU operation code */ 9700406dffSbellard #define MASK_PR 0x00080080 /* AU precision */ 9800406dffSbellard #define MASK_S1 0x00070000 /* AU source register 1 */ 9900406dffSbellard #define MASK_S2 0x00000007 /* AU source register 2 */ 10000406dffSbellard #define MASK_DS 0x00007000 /* AU destination register */ 10100406dffSbellard #define MASK_RM 0x00000060 /* AU rounding mode */ 10200406dffSbellard #define MASK_ALU 0x9cfff2ff /* only ALU can write these bits */ 10300406dffSbellard #define MASK_RESET 0x00000d00 /* bits set on reset, all others cleared */ 10400406dffSbellard #define MASK_WFC MASK_RESET 10500406dffSbellard #define MASK_RFC ~MASK_RESET 10600406dffSbellard 10700406dffSbellard #endif 108