interface/hvm/params.h

1 /* SPDX-License-Identifier: MIT */
34  * How should CPU0 event-channel notifications be delivered?
36  * If val == 0 then CPU0 event-channel notifications are not delivered.
62  * val[15:8] is interrupt flag of the PPI used by event-channel:
65  * val[7:0] is a PPI number used by event-channel.
74  * These are not used by Xen. They are here for convenience of HVM-guest
89 …* (See http://download.microsoft.com/download/A/B/4/AB43A34E-BDD0-4FA6-BDEF-79EEF16E880B/Hyperviso…
99  * - Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL)
100  * - APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR)
101  * - Virtual Processor index MSR (HV_X64_MSR_VP_INDEX)
102  * - Timer frequency MSRs (HV_X64_MSR_TSC_FREQUENCY and
118 /* Enable Partition Time Reference Counter (HV_X64_MSR_TIME_REF_COUNT) */
122 /* Enable Reference TSC Page (HV_X64_MSR_REFERENCE_TSC) */
134 /* Enable crash MSRs */
138 /* Enable SYNIC MSRs */
142 /* Enable STIMER MSRs */
150 /* Enable ExProcessorMasks */
158 /* Enable vCPU hotplug */
191  *   delivered at some non-zero rate, if we detect missed ticks then the
204 /* Boolean: Enable virtual HPET (high-precision event timer)? (x86-only) */
207 /* Identity-map page directory used by Intel EPT when CR0.PG=0. */
216 /* Boolean: Enable aligning all periodic vpts to reduce interrupts */
226  *   - 0: default, use the old addresses
228  *   - 1: use the new default qemu addresses
251  *  mixed: allow access to all altp2m ops for both in-guest and external tools
257  * security-critical environment, each subop should be evaluated for
273  * 8: save/restore 64-bit FIP/FDP and clear FCS/FDS (default if CPU
276  * 4: save/restore 32-bit FIP/FDP, FCS/FDS, and clear upper 32-bits of
294 /* Enable MCA capabilities. */