riscv: Set SBI_SUCCESS on successful DBCN call

Ensure we explicitly set SBI_SUCCESS on a successful SBI calls
since KVM will not initialize it to zero for us. Only DBCN was
neglecting to do so.

Fix

riscv: Set SBI_SUCCESS on successful DBCN call

Ensure we explicitly set SBI_SUCCESS on a successful SBI calls
since KVM will not initialize it to zero for us. Only DBCN was
neglecting to do so.

Fixes: 4ddaa4249e0c ("riscv: Handle SBI DBCN calls from Guest/VM")
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Link: https://lore.kernel.org/r/20240821142610.3297483-4-apatel@ventanamicro.com
Signed-off-by: Will Deacon <will@kernel.org>

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riscv: Add scalar crypto extensions support

When the scalar extensions are available expose them to the guest
via device tree so that guest can use it. This includes extensions
Zbkb, Zbkc, Zbkx, Zkn

riscv: Add scalar crypto extensions support

When the scalar extensions are available expose them to the guest
via device tree so that guest can use it. This includes extensions
Zbkb, Zbkc, Zbkx, Zknd, Zkne, Zknh, Zkr, Zksed, Zksh, and Zkt.

The Zkr extension requires SEED CSR emulation in user space so
we also add related KVM_EXIT_RISCV_CSR handling.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Link: https://lore.kernel.org/r/20240325153141.6816-5-apatel@ventanamicro.com
Signed-off-by: Will Deacon <will@kernel.org>

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riscv: Handle SBI DBCN calls from Guest/VM

The new SBI DBCN functions are forwarded by in-kernel KVM RISC-V module
to user-space so let us handle these calls in kvm_cpu_riscv_sbi() function.

Signed

riscv: Handle SBI DBCN calls from Guest/VM

The new SBI DBCN functions are forwarded by in-kernel KVM RISC-V module
to user-space so let us handle these calls in kvm_cpu_riscv_sbi() function.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Link: https://lore.kernel.org/r/20231128145628.413414-11-apatel@ventanamicro.com
Signed-off-by: Will Deacon <will@kernel.org>

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riscv: Allow disabling SBI extensions for Guest

We add "--disable-sbi-<xyz>" options to disable various SBI extensions
visible to the Guest. This allows users to disable deprecated/redundant
SBI ext

riscv: Allow disabling SBI extensions for Guest

We add "--disable-sbi-<xyz>" options to disable various SBI extensions
visible to the Guest. This allows users to disable deprecated/redundant
SBI extensions.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Link: https://lore.kernel.org/r/20230712163501.1769737-5-apatel@ventanamicro.com
Signed-off-by: Will Deacon <will@kernel.org>

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riscv: Allow setting custom mvendorid, marchid, and mimpid

We add command-line parameter to set custom mvendorid, marchid, and
mimpid so that users can show fake CPU type to Guest/VM which does
not

riscv: Allow setting custom mvendorid, marchid, and mimpid

We add command-line parameter to set custom mvendorid, marchid, and
mimpid so that users can show fake CPU type to Guest/VM which does
not match underlying Host CPU.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Link: https://lore.kernel.org/r/20230712163501.1769737-4-apatel@ventanamicro.com
Signed-off-by: Will Deacon <will@kernel.org>

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riscv: Move reg encoding helpers to kvm-cpu-arch.h

We'll need one of these helpers in the next patch in another file.
Let's proactively move them all now, since others may some day also
be useful.

riscv: Move reg encoding helpers to kvm-cpu-arch.h

We'll need one of these helpers in the next patch in another file.
Let's proactively move them all now, since others may some day also
be useful.

Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Link: https://lore.kernel.org/r/20221018140854.69846-5-apatel@ventanamicro.com
Signed-off-by: Will Deacon <will@kernel.org>

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riscv: Append ISA extensions to the device tree

The riscv,isa DT property only contains single letter base extensions
until now. However, there are also multi-letter extensions which were
ratified r

riscv: Append ISA extensions to the device tree

The riscv,isa DT property only contains single letter base extensions
until now. However, there are also multi-letter extensions which were
ratified recently. Add a mechanism to append those extension details
to the device tree so that guest can leverage those.

Signed-off-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Link: https://lore.kernel.org/r/20220815101325.477694-3-apatel@ventanamicro.com
Signed-off-by: Will Deacon <will@kernel.org>

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riscv: Handle SBI calls forwarded to user space

The kernel KVM RISC-V module will forward certain SBI calls
to user space. These forwared SBI calls will usually be the
SBI calls which cannot be emul

riscv: Handle SBI calls forwarded to user space

The kernel KVM RISC-V module will forward certain SBI calls
to user space. These forwared SBI calls will usually be the
SBI calls which cannot be emulated in kernel space such as
PUTCHAR and GETCHAR calls.

This patch extends kvm_cpu__handle_exit() to handle SBI calls
forwarded to user space.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Link: https://lore.kernel.org/r/20211119124515.89439-8-anup.patel@wdc.com
Signed-off-by: Will Deacon <will@kernel.org>

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riscv: Implement Guest/VM VCPU arch functions

This patch implements kvm_cpu__<xyz> Guest/VM VCPU arch functions.

These functions mostly deal with:
1. VCPU allocation and initialization
2. VCPU rese

riscv: Implement Guest/VM VCPU arch functions

This patch implements kvm_cpu__<xyz> Guest/VM VCPU arch functions.

These functions mostly deal with:
1. VCPU allocation and initialization
2. VCPU reset
3. VCPU show/dump code
4. VCPU show/dump registers

We also save RISC-V ISA, XLEN, and TIMEBASE frequency for each VCPU
so that it can be later used for generating Guest/VM FDT.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Link: https://lore.kernel.org/r/20211119124515.89439-5-anup.patel@wdc.com
Signed-off-by: Will Deacon <will@kernel.org>

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riscv: Initial skeletal support

This patch adds initial skeletal KVMTOOL RISC-V support which
just compiles for RV32 and RV64 host.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Link: https://lore

riscv: Initial skeletal support

This patch adds initial skeletal KVMTOOL RISC-V support which
just compiles for RV32 and RV64 host.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Link: https://lore.kernel.org/r/20211119124515.89439-3-anup.patel@wdc.com
Signed-off-by: Will Deacon <will@kernel.org>

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