1 #include "kvm/csr.h" 2 #include "kvm/kvm-cpu.h" 3 #include "kvm/kvm.h" 4 #include "kvm/virtio.h" 5 #include "kvm/sbi.h" 6 #include "kvm/term.h" 7 8 #include <asm/ptrace.h> 9 10 static int debug_fd; 11 12 void kvm_cpu__set_debug_fd(int fd) 13 { 14 debug_fd = fd; 15 } 16 17 int kvm_cpu__get_debug_fd(void) 18 { 19 return debug_fd; 20 } 21 22 struct kvm_cpu *kvm_cpu__arch_init(struct kvm *kvm, unsigned long cpu_id) 23 { 24 struct kvm_cpu *vcpu; 25 u64 timebase = 0; 26 unsigned long isa = 0, id = 0; 27 unsigned long masks[KVM_REG_RISCV_SBI_MULTI_REG_LAST + 1] = { 0 }; 28 int i, coalesced_offset, mmap_size; 29 struct kvm_one_reg reg; 30 31 vcpu = calloc(1, sizeof(struct kvm_cpu)); 32 if (!vcpu) 33 return NULL; 34 35 vcpu->vcpu_fd = ioctl(kvm->vm_fd, KVM_CREATE_VCPU, cpu_id); 36 if (vcpu->vcpu_fd < 0) 37 die_perror("KVM_CREATE_VCPU ioctl"); 38 39 reg.id = RISCV_CONFIG_REG(isa); 40 reg.addr = (unsigned long)&isa; 41 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 42 die("KVM_GET_ONE_REG failed (config.isa)"); 43 44 reg.id = RISCV_TIMER_REG(frequency); 45 reg.addr = (unsigned long)&timebase; 46 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 47 die("KVM_GET_ONE_REG failed (timer.frequency)"); 48 49 mmap_size = ioctl(kvm->sys_fd, KVM_GET_VCPU_MMAP_SIZE, 0); 50 if (mmap_size < 0) 51 die_perror("KVM_GET_VCPU_MMAP_SIZE ioctl"); 52 53 vcpu->kvm_run = mmap(NULL, mmap_size, PROT_RW, MAP_SHARED, 54 vcpu->vcpu_fd, 0); 55 if (vcpu->kvm_run == MAP_FAILED) 56 die("unable to mmap vcpu fd"); 57 58 coalesced_offset = ioctl(kvm->sys_fd, KVM_CHECK_EXTENSION, 59 KVM_CAP_COALESCED_MMIO); 60 if (coalesced_offset) 61 vcpu->ring = (void *)vcpu->kvm_run + 62 (coalesced_offset * PAGE_SIZE); 63 64 reg.id = RISCV_CONFIG_REG(isa); 65 reg.addr = (unsigned long)&isa; 66 if (ioctl(vcpu->vcpu_fd, KVM_SET_ONE_REG, ®) < 0) 67 die("KVM_SET_ONE_REG failed (config.isa)"); 68 69 if (kvm->cfg.arch.custom_mvendorid) { 70 id = kvm->cfg.arch.custom_mvendorid; 71 reg.id = RISCV_CONFIG_REG(mvendorid); 72 reg.addr = (unsigned long)&id; 73 if (ioctl(vcpu->vcpu_fd, KVM_SET_ONE_REG, ®) < 0) 74 die("KVM_SET_ONE_REG failed (config.mvendorid)"); 75 } 76 77 if (kvm->cfg.arch.custom_marchid) { 78 id = kvm->cfg.arch.custom_marchid; 79 reg.id = RISCV_CONFIG_REG(marchid); 80 reg.addr = (unsigned long)&id; 81 if (ioctl(vcpu->vcpu_fd, KVM_SET_ONE_REG, ®) < 0) 82 die("KVM_SET_ONE_REG failed (config.marchid)"); 83 } 84 85 if (kvm->cfg.arch.custom_mimpid) { 86 id = kvm->cfg.arch.custom_mimpid; 87 reg.id = RISCV_CONFIG_REG(mimpid); 88 reg.addr = (unsigned long)&id; 89 if (ioctl(vcpu->vcpu_fd, KVM_SET_ONE_REG, ®) < 0) 90 die("KVM_SET_ONE_REG failed (config.mimpid)"); 91 } 92 93 for (i = 0; i < KVM_RISCV_SBI_EXT_MAX; i++) { 94 if (!kvm->cfg.arch.sbi_ext_disabled[i]) 95 continue; 96 masks[KVM_REG_RISCV_SBI_MULTI_REG(i)] |= 97 KVM_REG_RISCV_SBI_MULTI_MASK(i); 98 } 99 for (i = 0; i <= KVM_REG_RISCV_SBI_MULTI_REG_LAST; i++) { 100 if (!masks[i]) 101 continue; 102 103 reg.id = RISCV_SBI_EXT_REG(KVM_REG_RISCV_SBI_MULTI_DIS, i); 104 reg.addr = (unsigned long)&masks[i]; 105 if (ioctl(vcpu->vcpu_fd, KVM_SET_ONE_REG, ®) < 0) 106 die("KVM_SET_ONE_REG failed (sbi_ext %d)", i); 107 } 108 109 /* Force enable SBI debug console if not disabled from command line */ 110 if (!kvm->cfg.arch.sbi_ext_disabled[KVM_RISCV_SBI_EXT_DBCN]) { 111 id = 1; 112 reg.id = RISCV_SBI_EXT_REG(KVM_REG_RISCV_SBI_SINGLE, 113 KVM_RISCV_SBI_EXT_DBCN); 114 reg.addr = (unsigned long)&id; 115 if (ioctl(vcpu->vcpu_fd, KVM_SET_ONE_REG, ®) < 0) 116 pr_warning("KVM_SET_ONE_REG failed (sbi_ext %d)", 117 KVM_RISCV_SBI_EXT_DBCN); 118 } 119 120 /* Populate the vcpu structure. */ 121 vcpu->kvm = kvm; 122 vcpu->cpu_id = cpu_id; 123 vcpu->riscv_isa = isa; 124 vcpu->riscv_xlen = __riscv_xlen; 125 vcpu->riscv_timebase = timebase; 126 vcpu->is_running = true; 127 128 return vcpu; 129 } 130 131 void kvm_cpu__arch_nmi(struct kvm_cpu *cpu) 132 { 133 } 134 135 void kvm_cpu__delete(struct kvm_cpu *vcpu) 136 { 137 free(vcpu); 138 } 139 140 static bool kvm_cpu_riscv_sbi(struct kvm_cpu *vcpu) 141 { 142 char ch; 143 u64 addr; 144 bool ret = true; 145 char *str_start, *str_end; 146 int dfd = kvm_cpu__get_debug_fd(); 147 148 switch (vcpu->kvm_run->riscv_sbi.extension_id) { 149 case SBI_EXT_0_1_CONSOLE_PUTCHAR: 150 ch = vcpu->kvm_run->riscv_sbi.args[0]; 151 term_putc(&ch, 1, 0); 152 vcpu->kvm_run->riscv_sbi.ret[0] = 0; 153 break; 154 case SBI_EXT_0_1_CONSOLE_GETCHAR: 155 if (term_readable(0)) 156 vcpu->kvm_run->riscv_sbi.ret[0] = 157 term_getc(vcpu->kvm, 0); 158 else 159 vcpu->kvm_run->riscv_sbi.ret[0] = SBI_ERR_FAILURE; 160 break; 161 case SBI_EXT_DBCN: 162 switch (vcpu->kvm_run->riscv_sbi.function_id) { 163 case SBI_EXT_DBCN_CONSOLE_WRITE: 164 case SBI_EXT_DBCN_CONSOLE_READ: 165 addr = vcpu->kvm_run->riscv_sbi.args[1]; 166 #if __riscv_xlen == 32 167 addr |= (u64)vcpu->kvm_run->riscv_sbi.args[2] << 32; 168 #endif 169 if (!vcpu->kvm_run->riscv_sbi.args[0]) 170 break; 171 str_start = guest_flat_to_host(vcpu->kvm, addr); 172 addr += vcpu->kvm_run->riscv_sbi.args[0] - 1; 173 str_end = guest_flat_to_host(vcpu->kvm, addr); 174 if (!str_start || !str_end) { 175 vcpu->kvm_run->riscv_sbi.ret[0] = 176 SBI_ERR_INVALID_PARAM; 177 break; 178 } 179 vcpu->kvm_run->riscv_sbi.ret[1] = 0; 180 while (str_start <= str_end) { 181 if (vcpu->kvm_run->riscv_sbi.function_id == 182 SBI_EXT_DBCN_CONSOLE_WRITE) { 183 term_putc(str_start, 1, 0); 184 } else { 185 if (!term_readable(0)) 186 break; 187 *str_start = term_getc(vcpu->kvm, 0); 188 } 189 vcpu->kvm_run->riscv_sbi.ret[1]++; 190 str_start++; 191 } 192 break; 193 case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: 194 ch = vcpu->kvm_run->riscv_sbi.args[0]; 195 term_putc(&ch, 1, 0); 196 vcpu->kvm_run->riscv_sbi.ret[0] = 0; 197 vcpu->kvm_run->riscv_sbi.ret[1] = 0; 198 break; 199 default: 200 vcpu->kvm_run->riscv_sbi.ret[0] = 201 SBI_ERR_NOT_SUPPORTED; 202 break; 203 } 204 break; 205 default: 206 dprintf(dfd, "Unhandled SBI call\n"); 207 dprintf(dfd, "extension_id=0x%lx function_id=0x%lx\n", 208 vcpu->kvm_run->riscv_sbi.extension_id, 209 vcpu->kvm_run->riscv_sbi.function_id); 210 dprintf(dfd, "args[0]=0x%lx args[1]=0x%lx\n", 211 vcpu->kvm_run->riscv_sbi.args[0], 212 vcpu->kvm_run->riscv_sbi.args[1]); 213 dprintf(dfd, "args[2]=0x%lx args[3]=0x%lx\n", 214 vcpu->kvm_run->riscv_sbi.args[2], 215 vcpu->kvm_run->riscv_sbi.args[3]); 216 dprintf(dfd, "args[4]=0x%lx args[5]=0x%lx\n", 217 vcpu->kvm_run->riscv_sbi.args[4], 218 vcpu->kvm_run->riscv_sbi.args[5]); 219 ret = false; 220 break; 221 }; 222 223 return ret; 224 } 225 226 static bool kvm_cpu_riscv_csr(struct kvm_cpu *vcpu) 227 { 228 int dfd = kvm_cpu__get_debug_fd(); 229 bool ret = true; 230 231 switch (vcpu->kvm_run->riscv_csr.csr_num) { 232 case CSR_SEED: 233 /* 234 * We ignore the new_value and write_mask and simply 235 * return a random value as SEED. 236 */ 237 vcpu->kvm_run->riscv_csr.ret_value = SEED_OPST_ES16; 238 vcpu->kvm_run->riscv_csr.ret_value |= rand() & SEED_ENTROPY_MASK; 239 break; 240 default: 241 dprintf(dfd, "Unhandled CSR access\n"); 242 dprintf(dfd, "csr_num=0x%lx new_value=0x%lx\n", 243 vcpu->kvm_run->riscv_csr.csr_num, 244 vcpu->kvm_run->riscv_csr.new_value); 245 dprintf(dfd, "write_mask=0x%lx ret_value=0x%lx\n", 246 vcpu->kvm_run->riscv_csr.write_mask, 247 vcpu->kvm_run->riscv_csr.ret_value); 248 ret = false; 249 break; 250 } 251 252 return ret; 253 } 254 255 bool kvm_cpu__handle_exit(struct kvm_cpu *vcpu) 256 { 257 switch (vcpu->kvm_run->exit_reason) { 258 case KVM_EXIT_RISCV_SBI: 259 return kvm_cpu_riscv_sbi(vcpu); 260 case KVM_EXIT_RISCV_CSR: 261 return kvm_cpu_riscv_csr(vcpu); 262 default: 263 break; 264 }; 265 266 return false; 267 } 268 269 void kvm_cpu__show_page_tables(struct kvm_cpu *vcpu) 270 { 271 } 272 273 void kvm_cpu__reset_vcpu(struct kvm_cpu *vcpu) 274 { 275 struct kvm *kvm = vcpu->kvm; 276 struct kvm_mp_state mp_state; 277 struct kvm_one_reg reg; 278 unsigned long data; 279 280 if (ioctl(vcpu->vcpu_fd, KVM_GET_MP_STATE, &mp_state) < 0) 281 die_perror("KVM_GET_MP_STATE failed"); 282 283 /* 284 * If MP state is stopped then it means Linux KVM RISC-V emulates 285 * SBI v0.2 (or higher) with HART power managment and give VCPU 286 * will power-up at boot-time by boot VCPU. For such VCPU, we 287 * don't update PC, A0 and A1 here. 288 */ 289 if (mp_state.mp_state == KVM_MP_STATE_STOPPED) 290 return; 291 292 reg.addr = (unsigned long)&data; 293 294 data = kvm->arch.kern_guest_start; 295 reg.id = RISCV_CORE_REG(regs.pc); 296 if (ioctl(vcpu->vcpu_fd, KVM_SET_ONE_REG, ®) < 0) 297 die_perror("KVM_SET_ONE_REG failed (pc)"); 298 299 data = vcpu->cpu_id; 300 reg.id = RISCV_CORE_REG(regs.a0); 301 if (ioctl(vcpu->vcpu_fd, KVM_SET_ONE_REG, ®) < 0) 302 die_perror("KVM_SET_ONE_REG failed (a0)"); 303 304 data = kvm->arch.dtb_guest_start; 305 reg.id = RISCV_CORE_REG(regs.a1); 306 if (ioctl(vcpu->vcpu_fd, KVM_SET_ONE_REG, ®) < 0) 307 die_perror("KVM_SET_ONE_REG failed (a1)"); 308 } 309 310 int kvm_cpu__get_endianness(struct kvm_cpu *vcpu) 311 { 312 return VIRTIO_ENDIAN_LE; 313 } 314 315 void kvm_cpu__show_code(struct kvm_cpu *vcpu) 316 { 317 struct kvm_one_reg reg; 318 unsigned long data; 319 int debug_fd = kvm_cpu__get_debug_fd(); 320 321 reg.addr = (unsigned long)&data; 322 323 dprintf(debug_fd, "\n*PC:\n"); 324 reg.id = RISCV_CORE_REG(regs.pc); 325 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 326 die("KVM_GET_ONE_REG failed (show_code @ PC)"); 327 328 kvm__dump_mem(vcpu->kvm, data, 32, debug_fd); 329 330 dprintf(debug_fd, "\n*RA:\n"); 331 reg.id = RISCV_CORE_REG(regs.ra); 332 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 333 die("KVM_GET_ONE_REG failed (show_code @ RA)"); 334 335 kvm__dump_mem(vcpu->kvm, data, 32, debug_fd); 336 } 337 338 static void kvm_cpu__show_csrs(struct kvm_cpu *vcpu) 339 { 340 struct kvm_one_reg reg; 341 struct kvm_riscv_csr csr; 342 unsigned long data; 343 int debug_fd = kvm_cpu__get_debug_fd(); 344 345 reg.addr = (unsigned long)&data; 346 dprintf(debug_fd, "\n Control Status Registers:\n"); 347 dprintf(debug_fd, " ------------------------\n"); 348 349 reg.id = RISCV_CSR_REG(sstatus); 350 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 351 die("KVM_GET_ONE_REG failed (sstatus)"); 352 csr.sstatus = data; 353 354 reg.id = RISCV_CSR_REG(sie); 355 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 356 die("KVM_GET_ONE_REG failed (sie)"); 357 csr.sie = data; 358 359 reg.id = RISCV_CSR_REG(stvec); 360 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 361 die("KVM_GET_ONE_REG failed (stvec)"); 362 csr.stvec = data; 363 364 reg.id = RISCV_CSR_REG(sip); 365 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 366 die("KVM_GET_ONE_REG failed (sip)"); 367 csr.sip = data; 368 369 reg.id = RISCV_CSR_REG(satp); 370 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 371 die("KVM_GET_ONE_REG failed (satp)"); 372 csr.satp = data; 373 374 reg.id = RISCV_CSR_REG(stval); 375 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 376 die("KVM_GET_ONE_REG failed (stval)"); 377 csr.stval = data; 378 379 reg.id = RISCV_CSR_REG(scause); 380 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 381 die("KVM_GET_ONE_REG failed (SCAUSE)"); 382 csr.scause = data; 383 384 reg.id = RISCV_CSR_REG(sscratch); 385 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 386 die("KVM_GET_ONE_REG failed (sscartch)"); 387 csr.sscratch = data; 388 dprintf(debug_fd, " SSTATUS: 0x%016lx\n", csr.sstatus); 389 dprintf(debug_fd, " SIE: 0x%016lx\n", csr.sie); 390 dprintf(debug_fd, " STVEC: 0x%016lx\n", csr.stvec); 391 dprintf(debug_fd, " SIP: 0x%016lx\n", csr.sip); 392 dprintf(debug_fd, " SATP: 0x%016lx\n", csr.satp); 393 dprintf(debug_fd, " STVAL: 0x%016lx\n", csr.stval); 394 dprintf(debug_fd, " SCAUSE: 0x%016lx\n", csr.scause); 395 dprintf(debug_fd, " SSCRATCH: 0x%016lx\n", csr.sscratch); 396 } 397 398 void kvm_cpu__show_registers(struct kvm_cpu *vcpu) 399 { 400 struct kvm_one_reg reg; 401 unsigned long data; 402 int debug_fd = kvm_cpu__get_debug_fd(); 403 struct kvm_riscv_core core; 404 405 reg.addr = (unsigned long)&data; 406 407 reg.id = RISCV_CORE_REG(mode); 408 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 409 die("KVM_GET_ONE_REG failed (mode)"); 410 core.mode = data; 411 412 reg.id = RISCV_CORE_REG(regs.pc); 413 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 414 die("KVM_GET_ONE_REG failed (pc)"); 415 core.regs.pc = data; 416 417 reg.id = RISCV_CORE_REG(regs.ra); 418 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 419 die("KVM_GET_ONE_REG failed (ra)"); 420 core.regs.ra = data; 421 422 reg.id = RISCV_CORE_REG(regs.sp); 423 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 424 die("KVM_GET_ONE_REG failed (sp)"); 425 core.regs.sp = data; 426 427 reg.id = RISCV_CORE_REG(regs.gp); 428 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 429 die("KVM_GET_ONE_REG failed (gp)"); 430 core.regs.gp = data; 431 432 reg.id = RISCV_CORE_REG(regs.tp); 433 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 434 die("KVM_GET_ONE_REG failed (tp)"); 435 core.regs.tp = data; 436 437 reg.id = RISCV_CORE_REG(regs.t0); 438 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 439 die("KVM_GET_ONE_REG failed (t0)"); 440 core.regs.t0 = data; 441 442 reg.id = RISCV_CORE_REG(regs.t1); 443 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 444 die("KVM_GET_ONE_REG failed (t1)"); 445 core.regs.t1 = data; 446 447 reg.id = RISCV_CORE_REG(regs.t2); 448 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 449 die("KVM_GET_ONE_REG failed (t2)"); 450 core.regs.t2 = data; 451 452 reg.id = RISCV_CORE_REG(regs.s0); 453 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 454 die("KVM_GET_ONE_REG failed (s0)"); 455 core.regs.s0 = data; 456 457 reg.id = RISCV_CORE_REG(regs.s1); 458 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 459 die("KVM_GET_ONE_REG failed (s1)"); 460 core.regs.s1 = data; 461 462 reg.id = RISCV_CORE_REG(regs.a0); 463 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 464 die("KVM_GET_ONE_REG failed (a0)"); 465 core.regs.a0 = data; 466 467 reg.id = RISCV_CORE_REG(regs.a1); 468 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 469 die("KVM_GET_ONE_REG failed (a1)"); 470 core.regs.a1 = data; 471 472 reg.id = RISCV_CORE_REG(regs.a2); 473 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 474 die("KVM_GET_ONE_REG failed (a2)"); 475 core.regs.a2 = data; 476 477 reg.id = RISCV_CORE_REG(regs.a3); 478 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 479 die("KVM_GET_ONE_REG failed (a3)"); 480 core.regs.a3 = data; 481 482 reg.id = RISCV_CORE_REG(regs.a4); 483 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 484 die("KVM_GET_ONE_REG failed (a4)"); 485 core.regs.a4 = data; 486 487 reg.id = RISCV_CORE_REG(regs.a5); 488 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 489 die("KVM_GET_ONE_REG failed (a5)"); 490 core.regs.a5 = data; 491 492 reg.id = RISCV_CORE_REG(regs.a6); 493 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 494 die("KVM_GET_ONE_REG failed (a6)"); 495 core.regs.a6 = data; 496 497 reg.id = RISCV_CORE_REG(regs.a7); 498 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 499 die("KVM_GET_ONE_REG failed (a7)"); 500 core.regs.a7 = data; 501 502 reg.id = RISCV_CORE_REG(regs.s2); 503 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 504 die("KVM_GET_ONE_REG failed (s2)"); 505 core.regs.s2 = data; 506 507 reg.id = RISCV_CORE_REG(regs.s3); 508 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 509 die("KVM_GET_ONE_REG failed (s3)"); 510 core.regs.s3 = data; 511 512 reg.id = RISCV_CORE_REG(regs.s4); 513 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 514 die("KVM_GET_ONE_REG failed (s4)"); 515 core.regs.s4 = data; 516 517 reg.id = RISCV_CORE_REG(regs.s5); 518 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 519 die("KVM_GET_ONE_REG failed (s5)"); 520 core.regs.s5 = data; 521 522 reg.id = RISCV_CORE_REG(regs.s6); 523 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 524 die("KVM_GET_ONE_REG failed (s6)"); 525 core.regs.s6 = data; 526 527 reg.id = RISCV_CORE_REG(regs.s7); 528 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 529 die("KVM_GET_ONE_REG failed (s7)"); 530 core.regs.s7 = data; 531 532 reg.id = RISCV_CORE_REG(regs.s8); 533 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 534 die("KVM_GET_ONE_REG failed (s8)"); 535 core.regs.s8 = data; 536 537 reg.id = RISCV_CORE_REG(regs.s9); 538 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 539 die("KVM_GET_ONE_REG failed (s9)"); 540 core.regs.s9 = data; 541 542 reg.id = RISCV_CORE_REG(regs.s10); 543 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 544 die("KVM_GET_ONE_REG failed (s10)"); 545 core.regs.s10 = data; 546 547 reg.id = RISCV_CORE_REG(regs.s11); 548 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 549 die("KVM_GET_ONE_REG failed (s11)"); 550 core.regs.s11 = data; 551 552 reg.id = RISCV_CORE_REG(regs.t3); 553 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 554 die("KVM_GET_ONE_REG failed (t3)"); 555 core.regs.t3 = data; 556 557 reg.id = RISCV_CORE_REG(regs.t4); 558 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 559 die("KVM_GET_ONE_REG failed (t4)"); 560 core.regs.t4 = data; 561 562 reg.id = RISCV_CORE_REG(regs.t5); 563 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 564 die("KVM_GET_ONE_REG failed (t5)"); 565 core.regs.t5 = data; 566 567 reg.id = RISCV_CORE_REG(regs.t6); 568 if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) 569 die("KVM_GET_ONE_REG failed (t6)"); 570 core.regs.t6 = data; 571 572 dprintf(debug_fd, "\n General Purpose Registers:\n"); 573 dprintf(debug_fd, " -------------------------\n"); 574 dprintf(debug_fd, " MODE: 0x%lx\n", data); 575 dprintf(debug_fd, " PC: 0x%016lx RA: 0x%016lx SP: 0x%016lx GP: 0x%016lx\n", 576 core.regs.pc, core.regs.ra, core.regs.sp, core.regs.gp); 577 dprintf(debug_fd, " TP: 0x%016lx T0: 0x%016lx T1: 0x%016lx T2: 0x%016lx\n", 578 core.regs.tp, core.regs.t0, core.regs.t1, core.regs.t2); 579 dprintf(debug_fd, " S0: 0x%016lx S1: 0x%016lx A0: 0x%016lx A1: 0x%016lx\n", 580 core.regs.s0, core.regs.s1, core.regs.a0, core.regs.a1); 581 dprintf(debug_fd, " A2: 0x%016lx A3: 0x%016lx A4: 0x%016lx A5: 0x%016lx\n", 582 core.regs.a2, core.regs.a3, core.regs.a4, core.regs.a5); 583 dprintf(debug_fd, " A6: 0x%016lx A7: 0x%016lx S2: 0x%016lx S3: 0x%016lx\n", 584 core.regs.a6, core.regs.a7, core.regs.s2, core.regs.s3); 585 dprintf(debug_fd, " S4: 0x%016lx S5: 0x%016lx S6: 0x%016lx S7: 0x%016lx\n", 586 core.regs.s4, core.regs.s5, core.regs.s6, core.regs.s7); 587 dprintf(debug_fd, " S8: 0x%016lx S9: 0x%016lx S10: 0x%016lx S11: 0x%016lx\n", 588 core.regs.s8, core.regs.s9, core.regs.s10, core.regs.s11); 589 dprintf(debug_fd, " T3: 0x%016lx T4: 0x%016lx T5: 0x%016lx T6: 0x%016lx\n", 590 core.regs.t3, core.regs.t4, core.regs.t5, core.regs.t6); 591 592 kvm_cpu__show_csrs(vcpu); 593 } 594