Searched +full:pwm +full:- +full:number (Results 1 – 17 of 17) sorted by relevance
2 * Nuvoton NPCM7xx PWM Module23 /* Each PWM module holds 4 PWM channels. */27 * Number of registers in one pwm module. Don't change this without increasing34 * cycles. For example, if NPCM7XX_PWM_MAX_DUTY=1,000,000 and a PWM has a duty35 * value of 100,000 the duty cycle for that PWM is 10%.42 * struct NPCM7xxPWM - The state of a single PWM channel.43 * @module: The PWM module that contains this channel.45 * @running: Whether this PWM channel is generating output.46 * @inverted: Whether this PWM channel is inverted.47 * @index: The index of this PWM channel.[all …]
2 * SiFive PWM34 #define TYPE_SIFIVE_PWM "sifive-pwm"50 * if en bit(s) set, is the number of ticks when pwmcount was 051 * if en bit(s) not set, is the number of ticks in pwmcount
20 #include "hw/core/split-irq.h"37 #include "hw/usb/hcd-ehci.h"38 #include "hw/usb/hcd-ohci.h"60 * PWM fan splitter. each splitter connects to one PWM output and93 NPCM7xxPWMState pwm[NPCM8XX_NR_PWM_MODULES]; member114 /* Number of CPU cores enabled in this SoC class. */122 * npcm8xx_load_kernel - Loads memory with everything needed to boot123 * @machine - The machine containing the SoC to be booted.124 * @soc - The SoC containing the CPU to be booted.
21 #include "hw/core/split-irq.h"37 #include "hw/usb/hcd-ehci.h"38 #include "hw/usb/hcd-ohci.h"60 * PWM fan splitter. each splitter connects to one PWM output and96 NPCM7xxPWMState pwm[NPCM7XX_NR_PWM_MODULES]; member124 /* Number of CPU cores enabled in this SoC class (may be 1 or 2). */129 * npcm7xx_load_kernel - Loads memory with everything needed to boot130 * @machine - The machine containing the SoC to be booted.131 * @soc - The SoC containing the CPU to be booted.
23 #include "hw/char/serial-mm.h"27 #include "hw/qdev-clock.h"28 #include "hw/qdev-properties.h"84 * Interrupt lines going into the GIC. This does not include internal Cortex-A35119 NPCM8XX_PWM0_IRQ = 93, /* PWM module 0 */120 NPCM8XX_PWM1_IRQ, /* PWM module 1 */175 /* Total number of GIC interrupts, including internal Cortex-A35 interrupts. */178 ((NPCM8XX_NUM_IRQ - GIC_INTERNAL) + (cpu) * GIC_INTERNAL)198 /* Direct memory-mapped access to SPI0 CS0-1. */204 /* Direct memory-mapped access to SPI1 CS0-3. */[all …]
21 #include "hw/char/serial-mm.h"24 #include "hw/qdev-clock.h"25 #include "hw/qdev-properties.h"30 #include "target/arm/cpu-qom.h"79 * Interrupt lines going into the GIC. This does not include internal Cortex-A9131 NPCM7XX_PWM0_IRQ = 93, /* PWM module 0 */132 NPCM7XX_PWM1_IRQ, /* PWM module 1 */153 /* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */171 /* Direct memory-mapped access to SPI0 CS0-1. */177 /* Direct memory-mapped access to SPI3 CS0-3. */[all …]
7 * the COPYING file in the top-level directory.14 #include "system/address-spaces.h"16 #include "hw/qdev-clock.h"93 [ASPEED_DEV_I3C] = 102, /* 102 -> 105 */95 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */107 return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]); in aspeed_soc_ast1030_get_irq()123 object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M); in aspeed_soc_ast1030_init()125 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); in aspeed_soc_ast1030_init()127 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); in aspeed_soc_ast1030_init()128 object_initialize_child(obj, "scu", &s->scu, typename); in aspeed_soc_ast1030_init()[all …]
35 #include "hw/qdev-properties.h"38 #include "hw/usb/hcd-ehci.h"39 #include "target/arm/cpu-qom.h"43 /* PWM */199 combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {200 /* int combiner groups 16-19 */244 /* groups 38-50 */252 /* groups 54-63 */259 ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq))290 /* Multi-core timer */[all …]
13 #include "hw/core/split-irq.h"23 #include "system/address-spaces.h"29 #include "hw/watchdog/cmsdk-apb-watchdog.h"32 #include "hw/timer/stellaris-gptm.h"33 #include "hw/qdev-clock.h"76 #define DEV_CAP(_dc, _cap) extract32(board->dc##_dc, DC##_dc##_##_cap, 1)92 #define TYPE_STELLARIS_SYS "stellaris-sys"113 /* Properties (all read-only registers) */127 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); in ssys_update()178 uint32_t did0 = s->did0; in ssys_board_class()[all …]
8 ARM1176JZF-S core, 512 MiB of RAM10 Cortex-A7 (4 cores), 1 GiB of RAM12 Cortex-A53 (4 cores), 512 MiB of RAM14 Cortex-A53 (4 cores), 1 GiB of RAM16 Cortex-A72 (4 cores), 2 GiB of RAM19 -------------------21 * ARM1176JZF-S, Cortex-A7, Cortex-A53 or Cortex-A72 CPU27 * Serial ports (BCM2835 AUX - 16550 based - and PL011)28 * Random Number Generator (RNG)41 ---------------[all …]
1 Nuvoton iBMC boards (``kudo-bmc``, ``mori-bmc``, ``npcm750-evb``, ``quanta-gbs-bmc``, ``quanta-gsj`…4 The `Nuvoton iBMC`_ chips are a family of Arm-based SoCs that are7 NPCM8XX series. NPCM7XX series feature one or two Arm Cortex-A9 CPU cores,8 while NPCM8XX feature 4 Arm Cortex-A35 CPU cores. Both series contain a12 .. _Nuvoton iBMC: https://www.nuvoton.com/products/cloud-computing/ibmc/14 The NPCM750 SoC has two Cortex-A9 cores and is targeted for the Enterprise17 - ``npcm750-evb`` Nuvoton NPCM750 Evaluation board19 The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and22 - ``quanta-gbs-bmc`` Quanta GBS server BMC23 - ``quanta-gsj`` Quanta GSJ server BMC[all …]
2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu15 * 5) OTP (One-Time Programmable) memory with stored serial number39 #include "qemu/error-report.h"99 uint64_t mem_size = ms->ram_size; in create_fdt()111 "sifive,plic-1.0.0", "riscv,plic0" in create_fdt()114 fdt = ms->fdt = create_device_tree(&s->fdt_size); in create_fdt()122 "sifive,hifive-unleashed-a00"); in create_fdt()123 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); in create_fdt()124 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); in create_fdt()[all …]
2 * QEMU DM163 8x3-channel constant current led driver6 * Copyright (C) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>7 * Copyright (C) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>9 * SPDX-License-Identifier: GPL-2.0-or-later21 #include "hw/qdev-properties.h"27 /* Number of frames a row stays visible after being turned off. */29 #define TURNED_OFF_ROW (COLOR_BUFFER_SIZE - 1)61 s->sin = 0; in dm163_reset_hold()62 s->dck = 0; in dm163_reset_hold()63 s->rst_b = 0; in dm163_reset_hold()[all …]
2 * SiFive PWM31 #include "hw/qdev-properties.h"72 return muldiv64(time, s->freq_hz, NANOSECONDS_PER_SECOND); in sifive_pwm_ns_to_ticks()78 return muldiv64(ticks, NANOSECONDS_PER_SECOND, s->freq_hz); in sifive_pwm_ticks_to_ns()83 return s->pwmcfg & R_CONFIG_SCALE_MASK; in sifive_pwm_compute_scale()90 if (HAS_PWM_EN_BITS(s->pwmcfg)) { in sifive_pwm_set_alarms()92 * Subtract ticks from number of ticks when the timer was zero in sifive_pwm_set_alarms()95 uint64_t pwmcount = (sifive_pwm_ns_to_ticks(s, now_ns) - in sifive_pwm_set_alarms()96 s->tick_offset) & PWMCOUNT_MASK; in sifive_pwm_set_alarms()102 uint64_t pwmcmp = s->pwmcmp[i] & PWMCMP_MASK; in sifive_pwm_set_alarms()[all …]
4 * Copyright (c) 2011-2018 Laurent Vivier5 * Copyright (c) 2018 Mark Cave-Ayland9 * Copyright (c) 2004-2007 Fabrice Bellard12 * some parts from linux-2.6.29, arch/m68k/include/asm/mac_via.h15 * See the COPYING file in the top-level directory.19 #include "system/address-spaces.h"30 #include "hw/qdev-properties.h"31 #include "hw/qdev-properties-system.h"32 #include "system/block-backend.h"77 * state-control line SEL" on all but IIfx[all …]
3 # allwinner-cpucfg.c8 # allwinner-h3-dramc.c18 # allwinner-r40-dramc.c32 # allwinner-sid.c36 # allwinner-sramc.c101 # mps2-scc.c108 # mps2-fpgaio.c113 # msf2-sysreg.c114 msf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev) "msf2-sysreg write: addr 0x%08" PRI…115 msf2_sysreg_read(uint64_t offset, uint32_t val) "msf2-sysreg read: addr 0x%08" PRIx64 " data 0x%08"…[all …]
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