Lines Matching +full:pwm +full:- +full:number
13 #include "hw/core/split-irq.h"
23 #include "system/address-spaces.h"
29 #include "hw/watchdog/cmsdk-apb-watchdog.h"
32 #include "hw/timer/stellaris-gptm.h"
33 #include "hw/qdev-clock.h"
76 #define DEV_CAP(_dc, _cap) extract32(board->dc##_dc, DC##_dc##_##_cap, 1)
92 #define TYPE_STELLARIS_SYS "stellaris-sys"
113 /* Properties (all read-only registers) */
127 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); in ssys_update()
178 uint32_t did0 = s->did0; in ssys_board_class()
204 return s->did0; in ssys_read()
206 return s->did1; in ssys_read()
208 return s->dc0; in ssys_read()
210 return s->dc1; in ssys_read()
212 return s->dc2; in ssys_read()
214 return s->dc3; in ssys_read()
216 return s->dc4; in ssys_read()
218 return s->pborctl; in ssys_read()
220 return s->ldopctl; in ssys_read()
228 return s->int_status; in ssys_read()
230 return s->int_mask; in ssys_read()
232 return s->int_status & s->int_mask; in ssys_read()
234 return s->resc; in ssys_read()
236 return s->rcc; in ssys_read()
240 xtal = (s->rcc >> 6) & 0xf; in ssys_read()
251 return s->rcc2; in ssys_read()
253 return s->rcgc[0]; in ssys_read()
255 return s->rcgc[1]; in ssys_read()
257 return s->rcgc[2]; in ssys_read()
259 return s->scgc[0]; in ssys_read()
261 return s->scgc[1]; in ssys_read()
263 return s->scgc[2]; in ssys_read()
265 return s->dcgc[0]; in ssys_read()
267 return s->dcgc[1]; in ssys_read()
269 return s->dcgc[2]; in ssys_read()
271 return s->clkvclr; in ssys_read()
273 return s->ldoarst; in ssys_read()
275 return s->user0; in ssys_read()
277 return s->user1; in ssys_read()
287 return (s->rcc2 >> 31) & 0x1; in ssys_use_rcc2()
293 * from migration post-load.
304 period_ns = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); in ssys_calculate_system_clock()
306 period_ns = 5 * (((s->rcc >> 23) & 0xf) + 1); in ssys_calculate_system_clock()
308 clock_set_ns(s->sysclk, period_ns); in ssys_calculate_system_clock()
310 clock_propagate(s->sysclk); in ssys_calculate_system_clock()
321 s->pborctl = value & 0xffff; in ssys_write()
324 s->ldopctl = value & 0x1f; in ssys_write()
332 s->int_mask = value & 0x7f; in ssys_write()
335 s->int_status &= ~value; in ssys_write()
338 s->resc = value & 0x3f; in ssys_write()
341 if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { in ssys_write()
343 s->int_status |= (1 << 6); in ssys_write()
345 s->rcc = value; in ssys_write()
353 if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { in ssys_write()
355 s->int_status |= (1 << 6); in ssys_write()
357 s->rcc2 = value; in ssys_write()
361 s->rcgc[0] = value; in ssys_write()
364 s->rcgc[1] = value; in ssys_write()
367 s->rcgc[2] = value; in ssys_write()
370 s->scgc[0] = value; in ssys_write()
373 s->scgc[1] = value; in ssys_write()
376 s->scgc[2] = value; in ssys_write()
379 s->dcgc[0] = value; in ssys_write()
382 s->dcgc[1] = value; in ssys_write()
385 s->dcgc[2] = value; in ssys_write()
388 s->clkvclr = value; in ssys_write()
391 s->ldoarst = value; in ssys_write()
410 s->pborctl = 0x7ffd; in stellaris_sys_reset_enter()
411 s->rcc = 0x078e3ac0; in stellaris_sys_reset_enter()
414 s->rcc2 = 0; in stellaris_sys_reset_enter()
416 s->rcc2 = 0x07802810; in stellaris_sys_reset_enter()
418 s->rcgc[0] = 1; in stellaris_sys_reset_enter()
419 s->scgc[0] = 1; in stellaris_sys_reset_enter()
420 s->dcgc[0] = 1; in stellaris_sys_reset_enter()
462 /* No field for sysclk -- handled in post-load instead */
484 memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000); in stellaris_sys_instance_init()
485 sysbus_init_mmio(sbd, &s->iomem); in stellaris_sys_instance_init()
486 sysbus_init_irq(sbd, &s->irq); in stellaris_sys_instance_init()
487 s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK"); in stellaris_sys_instance_init()
495 #define TYPE_STELLARIS_I2C "stellaris-i2c"
528 return s->msa; in stellaris_i2c_read()
531 return s->mcs | STELLARIS_I2C_MCS_IDLE; in stellaris_i2c_read()
533 return s->mdr; in stellaris_i2c_read()
535 return s->mtpr; in stellaris_i2c_read()
537 return s->mimr; in stellaris_i2c_read()
539 return s->mris; in stellaris_i2c_read()
541 return s->mris & s->mimr; in stellaris_i2c_read()
543 return s->mcr; in stellaris_i2c_read()
555 level = (s->mris & s->mimr) != 0; in stellaris_i2c_update()
556 qemu_set_irq(s->irq, level); in stellaris_i2c_update()
566 s->msa = value & 0xff; in stellaris_i2c_write()
569 if ((s->mcr & 0x10) == 0) { in stellaris_i2c_write()
574 if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { in stellaris_i2c_write()
575 if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) { in stellaris_i2c_write()
576 s->mcs |= STELLARIS_I2C_MCS_ARBLST; in stellaris_i2c_write()
578 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST; in stellaris_i2c_write()
579 s->mcs |= STELLARIS_I2C_MCS_BUSBSY; in stellaris_i2c_write()
583 if (!i2c_bus_busy(s->bus) in stellaris_i2c_write()
584 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { in stellaris_i2c_write()
585 s->mcs |= STELLARIS_I2C_MCS_ERROR; in stellaris_i2c_write()
588 s->mcs &= ~STELLARIS_I2C_MCS_ERROR; in stellaris_i2c_write()
592 if (s->msa & 1) { in stellaris_i2c_write()
594 s->mdr = i2c_recv(s->bus); in stellaris_i2c_write()
597 i2c_send(s->bus, s->mdr); in stellaris_i2c_write()
600 s->mris |= 1; in stellaris_i2c_write()
604 i2c_end_transfer(s->bus); in stellaris_i2c_write()
605 s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY; in stellaris_i2c_write()
609 s->mdr = value & 0xff; in stellaris_i2c_write()
612 s->mtpr = value & 0xff; in stellaris_i2c_write()
615 s->mimr = 1; in stellaris_i2c_write()
618 s->mris &= ~value; in stellaris_i2c_write()
629 s->mcr = value & 0x31; in stellaris_i2c_write()
642 if (s->mcs & STELLARIS_I2C_MCS_BUSBSY) in stellaris_i2c_reset_enter()
643 i2c_end_transfer(s->bus); in stellaris_i2c_reset_enter()
650 s->msa = 0; in stellaris_i2c_reset_hold()
651 s->mcs = 0; in stellaris_i2c_reset_hold()
652 s->mdr = 0; in stellaris_i2c_reset_hold()
653 s->mtpr = 1; in stellaris_i2c_reset_hold()
654 s->mimr = 0; in stellaris_i2c_reset_hold()
655 s->mris = 0; in stellaris_i2c_reset_hold()
656 s->mcr = 0; in stellaris_i2c_reset_hold()
695 sysbus_init_irq(sbd, &s->irq); in stellaris_i2c_init()
697 s->bus = bus; in stellaris_i2c_init()
699 memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s, in stellaris_i2c_init()
701 sysbus_init_mmio(sbd, &s->iomem); in stellaris_i2c_init()
718 #define TYPE_STELLARIS_ADC "stellaris-adc"
748 tail = s->fifo[n].state & 0xf; in stellaris_adc_fifo_read()
749 if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) { in stellaris_adc_fifo_read()
750 s->ustat |= 1 << n; in stellaris_adc_fifo_read()
752 s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf); in stellaris_adc_fifo_read()
753 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL; in stellaris_adc_fifo_read()
754 if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf)) in stellaris_adc_fifo_read()
755 s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY; in stellaris_adc_fifo_read()
757 return s->fifo[n].data[tail]; in stellaris_adc_fifo_read()
767 head = (s->fifo[n].state >> 4) & 0xf; in stellaris_adc_fifo_write()
768 if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) { in stellaris_adc_fifo_write()
769 s->ostat |= 1 << n; in stellaris_adc_fifo_write()
772 s->fifo[n].data[head] = value; in stellaris_adc_fifo_write()
774 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY; in stellaris_adc_fifo_write()
775 s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4); in stellaris_adc_fifo_write()
776 if ((s->fifo[n].state & 0xf) == head) in stellaris_adc_fifo_write()
777 s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL; in stellaris_adc_fifo_write()
786 level = (s->ris & s->im & (1 << n)) != 0; in stellaris_adc_update()
787 qemu_set_irq(s->irq[n], level); in stellaris_adc_update()
797 if ((s->actss & (1 << n)) == 0) { in stellaris_adc_trigger()
801 if (((s->emux >> (n * 4)) & 0xff) != 5) { in stellaris_adc_trigger()
805 /* Some applications use the ADC as a random number source, so introduce in stellaris_adc_trigger()
807 s->noise = s->noise * 314159 + 1; in stellaris_adc_trigger()
809 stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7)); in stellaris_adc_trigger()
810 s->ris |= (1 << n); in stellaris_adc_trigger()
821 s->ssmux[n] = 0; in stellaris_adc_reset_hold()
822 s->ssctl[n] = 0; in stellaris_adc_reset_hold()
823 s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY; in stellaris_adc_reset_hold()
835 n = (offset - 0x40) >> 5; in stellaris_adc_read()
838 return s->ssmux[n]; in stellaris_adc_read()
840 return s->ssctl[n]; in stellaris_adc_read()
844 return s->fifo[n].state; in stellaris_adc_read()
851 return s->actss; in stellaris_adc_read()
853 return s->ris; in stellaris_adc_read()
855 return s->im; in stellaris_adc_read()
857 return s->ris & s->im; in stellaris_adc_read()
859 return s->ostat; in stellaris_adc_read()
861 return s->emux; in stellaris_adc_read()
863 return s->ustat; in stellaris_adc_read()
865 return s->sspri; in stellaris_adc_read()
867 return s->sac; in stellaris_adc_read()
883 n = (offset - 0x40) >> 5; in stellaris_adc_write()
886 s->ssmux[n] = value & 0x33333333; in stellaris_adc_write()
894 s->ssctl[n] = value; in stellaris_adc_write()
902 s->actss = value & 0xf; in stellaris_adc_write()
905 s->im = value; in stellaris_adc_write()
908 s->ris &= ~value; in stellaris_adc_write()
911 s->ostat &= ~value; in stellaris_adc_write()
914 s->emux = value; in stellaris_adc_write()
917 s->ustat &= ~value; in stellaris_adc_write()
920 s->sspri = value; in stellaris_adc_write()
926 s->sac = value; in stellaris_adc_write()
983 sysbus_init_irq(sbd, &s->irq[n]); in stellaris_adc_init()
986 memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s, in stellaris_adc_init()
988 sysbus_init_mmio(sbd, &s->iomem); in stellaris_adc_init()
1045 * 40028000 PWM (unimplemented) in stellaris_init()
1079 flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024; in stellaris_init()
1080 sram_size = ((board->dc0 >> 18) + 1) * 1024; in stellaris_init()
1095 * Create the system-registers object early, because we will in stellaris_init()
1103 * Generate a MAC address now, if there isn't a matching -nic for it. in stellaris_init()
1107 memcpy(mac.a, nd->macaddr.a, sizeof(mac.a)); in stellaris_init()
1116 qdev_prop_set_uint32(ssys_dev, "did0", board->did0); in stellaris_init()
1117 qdev_prop_set_uint32(ssys_dev, "did1", board->did1); in stellaris_init()
1118 qdev_prop_set_uint32(ssys_dev, "dc0", board->dc0); in stellaris_init()
1119 qdev_prop_set_uint32(ssys_dev, "dc1", board->dc1); in stellaris_init()
1120 qdev_prop_set_uint32(ssys_dev, "dc2", board->dc2); in stellaris_init()
1121 qdev_prop_set_uint32(ssys_dev, "dc3", board->dc3); in stellaris_init()
1122 qdev_prop_set_uint32(ssys_dev, "dc4", board->dc4); in stellaris_init()
1127 qdev_prop_set_uint32(armv7m, "num-irq", NUM_IRQ_LINES); in stellaris_init()
1128 qdev_prop_set_uint8(armv7m, "num-prio-bits", NUM_PRIO_BITS); in stellaris_init()
1129 qdev_prop_set_string(armv7m, "cpu-type", ms->cpu_type); in stellaris_init()
1130 qdev_prop_set_bit(armv7m, "enable-bitband", true); in stellaris_init()
1208 if (board->peripherals & BP_OLED_I2C) { in stellaris_init()
1230 if (board->peripherals & BP_OLED_SSI) { in stellaris_init()
1249 * - GPIO pin D0 is wired to the active-low SD card chip select in stellaris_init()
1250 * - GPIO pin A3 is wired to the active-low OLED chip select in stellaris_init()
1251 * - The SoC wiring of the PL061 "auxiliary function" for A3 is in stellaris_init()
1254 * transmits a frame, so it can work as a chip-select signal. in stellaris_init()
1255 * - GPIO A4 is aux-function SSI0Rx, and wired to the SD card Tx in stellaris_init()
1257 * - GPIO A5 is aux-function SSI0Tx, and wired to the SD card Rx in stellaris_init()
1258 * and the OLED display-data-in in stellaris_init()
1259 * - GPIO A2 is aux-function SSI0Clk, wired to SD card and OLED in stellaris_init()
1260 * serial-clock input in stellaris_init()
1262 * to make pins A2, A3, A5 aux-function, so they are connected in stellaris_init()
1266 * as aux-function, but leaves A3 as a software-controlled GPIO in stellaris_init()
1267 * line. It asserts the SD card chip-select by using the PL061 in stellaris_init()
1270 * usual, but because A3 is not set to aux-function this is not in stellaris_init()
1274 * - GPIO pin D0 is wired to the active-low SD card chip select, in stellaris_init()
1275 * and also to the OLED chip-select which is implemented in stellaris_init()
1276 * as *active-high* in stellaris_init()
1277 * - SSI controller signals go to the devices regardless of in stellaris_init()
1278 * whether the guest programs A2, A4, A5 as aux-function or not in stellaris_init()
1286 * never gets the chip-select assert it needs. We work around in stellaris_init()
1292 * - Implement aux-function support in the PL061, with an in stellaris_init()
1296 * - Wire the AFOUT for D0 up to either a line from the in stellaris_init()
1298 * or at least to an always-0 line here on the board in stellaris_init()
1299 * - Make the ssd0323 OLED controller chipselect active-low in stellaris_init()
1302 sddev = ssi_create_peripheral(bus, "ssi-sd"); in stellaris_init()
1309 qdev_get_child_bus(sddev, "sd-bus"), in stellaris_init()
1320 qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2); in stellaris_init()
1351 if (board->peripherals & BP_GAMEPAD) { in stellaris_init()
1379 if (board->dc4 & (1 << i)) { in stellaris_init()
1391 create_unimplemented_device("PWM", 0x40028000, 0x1000); in stellaris_init()
1392 create_unimplemented_device("QEI-0", 0x4002c000, 0x1000); in stellaris_init()
1393 create_unimplemented_device("QEI-1", 0x4002d000, 0x1000); in stellaris_init()
1394 create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000); in stellaris_init()
1396 create_unimplemented_device("flash-control", 0x400fd000, 0x1000); in stellaris_init()
1398 armv7m_load_kernel(ARMV7M(armv7m)->cpu, ms->kernel_filename, 0, flash_size); in stellaris_init()
1420 mc->desc = "Stellaris LM3S811EVB (Cortex-M3)"; in lm3s811evb_class_init()
1421 mc->init = lm3s811evb_init; in lm3s811evb_class_init()
1422 mc->ignore_memory_transaction_failures = true; in lm3s811evb_class_init()
1423 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); in lm3s811evb_class_init()
1440 mc->desc = "Stellaris LM3S6965EVB (Cortex-M3)"; in lm3s6965evb_class_init()
1441 mc->init = lm3s6965evb_init; in lm3s6965evb_class_init()
1442 mc->ignore_memory_transaction_failures = true; in lm3s6965evb_class_init()
1443 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); in lm3s6965evb_class_init()
1444 mc->auto_create_sdcard = true; in lm3s6965evb_class_init()
1466 rc->phases.enter = stellaris_i2c_reset_enter; in type_init()
1467 rc->phases.hold = stellaris_i2c_reset_hold; in type_init()
1468 rc->phases.exit = stellaris_i2c_reset_exit; in type_init()
1469 dc->vmsd = &vmstate_stellaris_i2c; in type_init()
1485 rc->phases.hold = stellaris_adc_reset_hold; in stellaris_adc_class_init()
1486 dc->vmsd = &vmstate_stellaris_adc; in stellaris_adc_class_init()
1502 dc->vmsd = &vmstate_stellaris_sys; in stellaris_sys_class_init()
1503 rc->phases.enter = stellaris_sys_reset_enter; in stellaris_sys_class_init()
1504 rc->phases.hold = stellaris_sys_reset_hold; in stellaris_sys_class_init()
1505 rc->phases.exit = stellaris_sys_reset_exit; in stellaris_sys_class_init()