1 /* 2 * Nuvoton NPCM8xx SoC family. 3 * 4 * Copyright 2022 Google LLC 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 */ 16 #ifndef NPCM8XX_H 17 #define NPCM8XX_H 18 19 #include "hw/adc/npcm7xx_adc.h" 20 #include "hw/core/split-irq.h" 21 #include "hw/cpu/cluster.h" 22 #include "hw/gpio/npcm7xx_gpio.h" 23 #include "hw/i2c/npcm7xx_smbus.h" 24 #include "hw/intc/arm_gic_common.h" 25 #include "hw/mem/npcm7xx_mc.h" 26 #include "hw/misc/npcm_clk.h" 27 #include "hw/misc/npcm_gcr.h" 28 #include "hw/misc/npcm7xx_mft.h" 29 #include "hw/misc/npcm7xx_pwm.h" 30 #include "hw/misc/npcm7xx_rng.h" 31 #include "hw/net/npcm_gmac.h" 32 #include "hw/net/npcm_pcs.h" 33 #include "hw/nvram/npcm7xx_otp.h" 34 #include "hw/sd/npcm7xx_sdhci.h" 35 #include "hw/timer/npcm7xx_timer.h" 36 #include "hw/ssi/npcm7xx_fiu.h" 37 #include "hw/usb/hcd-ehci.h" 38 #include "hw/usb/hcd-ohci.h" 39 #include "target/arm/cpu.h" 40 #include "hw/ssi/npcm_pspi.h" 41 42 #define NPCM8XX_MAX_NUM_CPUS (4) 43 44 /* The first half of the address space is reserved for DDR4 DRAM. */ 45 #define NPCM8XX_DRAM_BA (0x00000000) 46 #define NPCM8XX_DRAM_SZ (2 * GiB) 47 48 /* Magic addresses for setting up direct kernel booting and SMP boot stubs. */ 49 #define NPCM8XX_LOADER_START (0x00000000) /* Start of SDRAM */ 50 #define NPCM8XX_SMP_LOADER_START (0xffff0000) /* Boot ROM */ 51 #define NPCM8XX_SMP_BOOTREG_ADDR (0xf080013c) /* GCR.SCRPAD */ 52 #define NPCM8XX_BOARD_SETUP_ADDR (0xffff1000) /* Boot ROM */ 53 54 #define NPCM8XX_NR_PWM_MODULES 3 55 56 struct NPCM8xxMachine { 57 MachineState parent_obj; 58 59 /* 60 * PWM fan splitter. each splitter connects to one PWM output and 61 * multiple MFT inputs. 62 */ 63 SplitIRQ fan_splitter[NPCM8XX_NR_PWM_MODULES * 64 NPCM7XX_PWM_PER_MODULE]; 65 }; 66 67 68 struct NPCM8xxMachineClass { 69 MachineClass parent_class; 70 71 const char *soc_type; 72 }; 73 74 #define TYPE_NPCM8XX_MACHINE MACHINE_TYPE_NAME("npcm8xx") 75 OBJECT_DECLARE_TYPE(NPCM8xxMachine, NPCM8xxMachineClass, NPCM8XX_MACHINE) 76 77 struct NPCM8xxState { 78 DeviceState parent_obj; 79 80 ARMCPU cpu[NPCM8XX_MAX_NUM_CPUS]; 81 CPUClusterState cpu_cluster; 82 GICState gic; 83 84 MemoryRegion sram; 85 MemoryRegion irom; 86 MemoryRegion ram3; 87 MemoryRegion *dram; 88 89 NPCMGCRState gcr; 90 NPCMCLKState clk; 91 NPCM7xxTimerCtrlState tim[3]; 92 NPCM7xxADCState adc; 93 NPCM7xxPWMState pwm[NPCM8XX_NR_PWM_MODULES]; 94 NPCM7xxMFTState mft[8]; 95 NPCM7xxOTPState fuse_array; 96 NPCM7xxMCState mc; 97 NPCM7xxRNGState rng; 98 NPCM7xxGPIOState gpio[8]; 99 NPCM7xxSMBusState smbus[27]; 100 EHCISysBusState ehci[2]; 101 OHCISysBusState ohci[2]; 102 NPCM7xxFIUState fiu[3]; 103 NPCMGMACState gmac[4]; 104 NPCMPCSState pcs; 105 NPCM7xxSDHCIState mmc; 106 NPCMPSPIState pspi; 107 }; 108 109 struct NPCM8xxClass { 110 DeviceClass parent_class; 111 112 /* Bitmask of modules that are permanently disabled on this chip. */ 113 uint32_t disabled_modules; 114 /* Number of CPU cores enabled in this SoC class. */ 115 uint32_t num_cpus; 116 }; 117 118 #define TYPE_NPCM8XX "npcm8xx" 119 OBJECT_DECLARE_TYPE(NPCM8xxState, NPCM8xxClass, NPCM8XX) 120 121 /** 122 * npcm8xx_load_kernel - Loads memory with everything needed to boot 123 * @machine - The machine containing the SoC to be booted. 124 * @soc - The SoC containing the CPU to be booted. 125 * 126 * This will set up the ARM boot info structure for the specific NPCM8xx 127 * derivative and call arm_load_kernel() to set up loading of the kernel, etc. 128 * into memory, if requested by the user. 129 */ 130 void npcm8xx_load_kernel(MachineState *machine, NPCM8xxState *soc); 131 132 #endif /* NPCM8XX_H */ 133