Searched full:lower (Results 1 – 16 of 16) sorted by relevance
45 * lower bits are addresses). But with AMD SEV enabled, the upper bound is one46 * bit lower than the c-bit position.
13 * leaving the lower status codes for unit tests.
19 $(shell echo $(notdir $(1)) | tr [:lower:]- [:upper:]_)
61 "lower 32 bits modified"); in test_epsw()
55 * Only the lower seven bits of the seed are considered.
173 * Prefixing should not work with large pages. Since the lower in test_edat1()
32 #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
98 /* lower IPI */ in extint_handler()
244 * smaller pages existed, all the lower tables are freed.
448 report(g_isr_64 == 1 && d.remote_irr == 0, "Reconfigure self lower priority"); in test_ioapic_self_reconfigure()
384 * want different walks to merge at lower levels. in __ac_test_init()444 * being able to detect a bug are even lower. in ac_test_legal()
546 * while RAX hold its lower 32 bits. in msr_intercept_finished()1775 // Set irq to lower priority in virq_inject_finished()2507 * The VMRUN instruction ignores the lower 12 bits of the address specified
241 * overwrite the lower boundary of branch misses event to 0 to avoid in adjust_events_range()
5337 * - The lower 4 bits of the VM-entry MSR-load address must be 0.5463 * - The lower 4 bits of the VM-exit MSR-store address must be 0.6828 * When L1's TPR is passed through to L2, the lower in test_x2apic_wr()6832 * Here's how the lower nibble can get lost: in test_x2apic_wr()6842 * clears the lower nibble of L1's TPR. in test_x2apic_wr()
928 report(sse_event_pending(next->event_id), "Lower priority event is pending"); in sse_low_priority_test_handler()930 "Lower priority event %s was not handled before %s", in sse_low_priority_test_handler()
303 #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */