1d9193a9cSWei Huang #ifndef _ASMARM_SYSREG_H_ 2d9193a9cSWei Huang #define _ASMARM_SYSREG_H_ 3d3aacb4fSAndrew Jones /* 4d3aacb4fSAndrew Jones * From the Linux kernel arch/arm/include/asm/cp15.h 5d3aacb4fSAndrew Jones * 649f758b8SAndrew Jones * This work is licensed under the terms of the GNU GPL, version 2. 749f758b8SAndrew Jones */ 849f758b8SAndrew Jones 949f758b8SAndrew Jones /* 10d3aacb4fSAndrew Jones * CR1 bits (CP#15 CR1) 11d3aacb4fSAndrew Jones */ 12d3aacb4fSAndrew Jones #define CR_M (1 << 0) /* MMU enable */ 13d3aacb4fSAndrew Jones #define CR_A (1 << 1) /* Alignment abort enable */ 14d3aacb4fSAndrew Jones #define CR_C (1 << 2) /* Dcache enable */ 15d3aacb4fSAndrew Jones #define CR_W (1 << 3) /* Write buffer enable */ 16d3aacb4fSAndrew Jones #define CR_P (1 << 4) /* 32-bit exception handler */ 17d3aacb4fSAndrew Jones #define CR_D (1 << 5) /* 32-bit data address range */ 18d3aacb4fSAndrew Jones #define CR_L (1 << 6) /* Implementation defined */ 19d3aacb4fSAndrew Jones #define CR_B (1 << 7) /* Big endian */ 20d3aacb4fSAndrew Jones #define CR_S (1 << 8) /* System MMU protection */ 21d3aacb4fSAndrew Jones #define CR_R (1 << 9) /* ROM MMU protection */ 22d3aacb4fSAndrew Jones #define CR_F (1 << 10) /* Implementation defined */ 23d3aacb4fSAndrew Jones #define CR_Z (1 << 11) /* Implementation defined */ 24d3aacb4fSAndrew Jones #define CR_I (1 << 12) /* Icache enable */ 25d3aacb4fSAndrew Jones #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */ 26d3aacb4fSAndrew Jones #define CR_RR (1 << 14) /* Round Robin cache replacement */ 27d3aacb4fSAndrew Jones #define CR_L4 (1 << 15) /* LDR pc can set T bit */ 28d3aacb4fSAndrew Jones #define CR_DT (1 << 16) 29d3aacb4fSAndrew Jones #define CR_HA (1 << 17) /* Hardware management of Access Flag */ 30d3aacb4fSAndrew Jones #define CR_IT (1 << 18) 31d3aacb4fSAndrew Jones #define CR_ST (1 << 19) 32d3aacb4fSAndrew Jones #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */ 33d3aacb4fSAndrew Jones #define CR_U (1 << 22) /* Unaligned access operation */ 34d3aacb4fSAndrew Jones #define CR_XP (1 << 23) /* Extended page tables */ 35d3aacb4fSAndrew Jones #define CR_VE (1 << 24) /* Vectored interrupts */ 36d3aacb4fSAndrew Jones #define CR_EE (1 << 25) /* Exception (Big) Endian */ 37d3aacb4fSAndrew Jones #define CR_TRE (1 << 28) /* TEX remap enable */ 38d3aacb4fSAndrew Jones #define CR_AFE (1 << 29) /* Access flag enable */ 39d3aacb4fSAndrew Jones #define CR_TE (1 << 30) /* Thumb exception enable */ 40d3aacb4fSAndrew Jones 41*0cc3a351SSean Christopherson #ifndef __ASSEMBLER__ 4292fca209SWei Huang #include <libcflat.h> 4392fca209SWei Huang 4492fca209SWei Huang #define __ACCESS_CP15(CRn, Op1, CRm, Op2) \ 4592fca209SWei Huang "mrc", "mcr", xstr(p15, Op1, %0, CRn, CRm, Op2), u32 4692fca209SWei Huang #define __ACCESS_CP15_64(Op1, CRm) \ 4792fca209SWei Huang "mrrc", "mcrr", xstr(p15, Op1, %Q0, %R0, CRm), u64 4892fca209SWei Huang 4998cbd390SAlex Bennée #define __ACCESS_CP14(CRn, Op1, CRm, Op2) \ 5098cbd390SAlex Bennée "mrc", "mcr", xstr(p14, Op1, %0, CRn, CRm, Op2), u32 5198cbd390SAlex Bennée #define __ACCESS_CP14_64(Op1, CRm) \ 5298cbd390SAlex Bennée "mrrc", "mcrr", xstr(p14, Op1, %Q0, %R0, CRm), u64 5398cbd390SAlex Bennée 5492fca209SWei Huang #define __read_sysreg(r, w, c, t) ({ \ 5592fca209SWei Huang t __val; \ 5692fca209SWei Huang asm volatile(r " " c : "=r" (__val)); \ 5792fca209SWei Huang __val; \ 5892fca209SWei Huang }) 5992fca209SWei Huang #define read_sysreg(...) __read_sysreg(__VA_ARGS__) 6092fca209SWei Huang 6192fca209SWei Huang #define __write_sysreg(v, r, w, c, t) asm volatile(w " " c : : "r" ((t)(v))) 6292fca209SWei Huang #define write_sysreg(v, ...) __write_sysreg(v, __VA_ARGS__) 63*0cc3a351SSean Christopherson #endif /* !__ASSEMBLER__ */ 6492fca209SWei Huang 65d9193a9cSWei Huang #endif /* _ASMARM_SYSREG_H_ */ 66