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Searched refs:dma (Results 1 – 25 of 78) sorted by relevance

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/qemu/hw/dma/
H A Dsoc_dma.c89 struct dma_s *dma = (struct dma_s *) ch->dma; in soc_dma_ch_schedule() local
91 timer_mod(ch->timer, now + delay_bytes / dma->channel_freq); in soc_dma_ch_schedule()
99 ch->dma->setup_fn(ch); in soc_dma_ch_run()
108 static inline struct memmap_entry_s *soc_dma_lookup(struct dma_s *dma, in soc_dma_lookup() argument
114 lo = dma->memmap; in soc_dma_lookup()
115 hi = dma->memmap_size; in soc_dma_lookup()
129 struct dma_s *dma = (struct dma_s *) ch->dma; in soc_dma_ch_update_type() local
130 struct memmap_entry_s *entry = soc_dma_lookup(dma, ch->vaddr[port]); in soc_dma_ch_update_type()
133 while (entry < dma->memmap + dma->memmap_size && in soc_dma_ch_update_type()
171 ch->transfer_fn = ch->dma->transfer_fn; in soc_dma_ch_update()
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H A Domap_dma.c93 struct soc_dma_ch_s *dma; member
105 struct soc_dma_s *dma; member
204 ch->dma->type[i] = soc_dma_access_const; in omap_dma_channel_load()
207 ch->dma->type[i] = soc_dma_access_linear; in omap_dma_channel_load()
209 ch->dma->type[i] = soc_dma_access_other; in omap_dma_channel_load()
211 ch->dma->vaddr[i] = ch->addr[i]; in omap_dma_channel_load()
213 soc_dma_ch_update(ch->dma); in omap_dma_channel_load()
232 soc_dma_set_request(ch->dma, 1); in omap_dma_activate_channel()
252 if (ch->sync && ch->enable && (s->dma->drqbmp & (1ULL << ch->sync))) in omap_dma_deactivate_channel()
258 soc_dma_set_request(ch->dma, 0); in omap_dma_deactivate_channel()
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H A Dxilinx_axidma.c108 struct XilinxAXIDMA *dma; member
125 struct XilinxAXIDMA *dma; member
201 MemTxResult result = address_space_read(&s->dma->as, in stream_desc_load()
236 address_space_write(&s->dma->as, addr, MEMTXATTRS_UNSPECIFIED, in stream_desc_store()
324 address_space_read(&s->dma->as, addr, in stream_process_mem2s()
377 address_space_write(&s->dma->as, s->desc.buffer_address, in stream_process_s2mem()
421 struct Stream *s = &cs->dma->streams[1]; in xilinx_axidma_control_stream_push()
438 struct Stream *s = &ds->dma->streams[1]; in xilinx_axidma_data_stream_can_push()
441 ds->dma->notify = notify; in xilinx_axidma_data_stream_can_push()
442 ds->dma->notify_opaque = notify_opaque; in xilinx_axidma_data_stream_can_push()
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/qemu/hw/display/
H A Domap_lcdc.c45 struct omap_dma_lcd_channel_s *dma; member
220 omap_lcd->dma->phys_framebuffer[omap_lcd->dma->current_frame], in omap_update_display()
271 if (omap_lcd->dma->current_frame == 0) in omap_update_display()
272 size = omap_lcd->dma->src_f1_bottom - omap_lcd->dma->src_f1_top; in omap_update_display()
274 size = omap_lcd->dma->src_f2_bottom - omap_lcd->dma->src_f2_top; in omap_update_display()
284 frame_base = omap_lcd->dma->phys_framebuffer[ in omap_update_display()
285 omap_lcd->dma->current_frame] + frame_offset; in omap_update_display()
286 omap_lcd->dma->condition |= 1 << omap_lcd->dma->current_frame; in omap_update_display()
287 if (omap_lcd->dma->interrupts & 1) in omap_update_display()
288 qemu_irq_raise(omap_lcd->dma->irq); in omap_update_display()
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/qemu/hw/misc/
H A Dedu.c74 } dma; member
145 if (!(edu->dma.cmd & EDU_DMA_RUN)) { in edu_dma_timer()
149 if (EDU_DMA_DIR(edu->dma.cmd) == EDU_DMA_FROM_PCI) { in edu_dma_timer()
150 uint64_t dst = edu->dma.dst; in edu_dma_timer()
151 edu_check_range(dst, edu->dma.cnt, DMA_START, DMA_SIZE); in edu_dma_timer()
153 pci_dma_read(&edu->pdev, edu_clamp_addr(edu, edu->dma.src), in edu_dma_timer()
154 edu->dma_buf + dst, edu->dma.cnt); in edu_dma_timer()
156 uint64_t src = edu->dma.src; in edu_dma_timer()
157 edu_check_range(src, edu->dma.cnt, DMA_START, DMA_SIZE); in edu_dma_timer()
159 pci_dma_write(&edu->pdev, edu_clamp_addr(edu, edu->dma.dst), in edu_dma_timer()
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/qemu/hw/ppc/
H A Dppc440_uc.c539 PPC4xxDmaState *dma = opaque; in dcr_read_dma() local
541 int addr = dcrn - dma->base; in dcr_read_dma()
548 val = dma->ch[chnl].cr; in dcr_read_dma()
551 val = dma->ch[chnl].ct; in dcr_read_dma()
554 val = dma->ch[chnl].sa >> 32; in dcr_read_dma()
557 val = dma->ch[chnl].sa; in dcr_read_dma()
560 val = dma->ch[chnl].da >> 32; in dcr_read_dma()
563 val = dma->ch[chnl].da; in dcr_read_dma()
566 val = dma->ch[chnl].sg >> 32; in dcr_read_dma()
569 val = dma->ch[chnl].sg; in dcr_read_dma()
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/qemu/hw/riscv/
H A Dmicroblaze-v-generic.c57 DeviceState *dev, *dma, *eth0; in mb_v_generic_init() local
136 dma = qdev_new("xlnx.axi-dma"); in mb_v_generic_init()
140 object_property_add_child(qdev_get_machine(), "xilinx-dma", OBJECT(dma)); in mb_v_generic_init()
142 ds = object_property_get_link(OBJECT(dma), in mb_v_generic_init()
144 cs = object_property_get_link(OBJECT(dma), in mb_v_generic_init()
161 qdev_prop_set_uint32(dma, "freqhz", 100000000); in mb_v_generic_init()
162 object_property_set_link(OBJECT(dma), "axistream-connected", ds, in mb_v_generic_init()
164 object_property_set_link(OBJECT(dma), "axistream-control-connected", cs, in mb_v_generic_init()
166 sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal); in mb_v_generic_init()
167 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, AXIDMA_BASEADDR); in mb_v_generic_init()
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/qemu/hw/m68k/
H A Dnext-cube.c145 next_dma dma[10]; member
311 next_state->dma[NEXTDMA_ENRX].csr |= DMA_DEV2M; in next_dma_write()
316 next_state->dma[NEXTDMA_ENRX].csr |= DMA_ENABLE; in next_dma_write()
319 next_state->dma[NEXTDMA_ENRX].csr |= DMA_SUPDATE; in next_dma_write()
322 next_state->dma[NEXTDMA_ENRX].csr &= ~DMA_COMPLETE; in next_dma_write()
326 next_state->dma[NEXTDMA_ENRX].csr &= ~(DMA_COMPLETE | DMA_SUPDATE | in next_dma_write()
333 next_state->dma[NEXTDMA_ENRX].next_initbuf = val; in next_dma_write()
337 next_state->dma[NEXTDMA_ENRX].next = val; in next_dma_write()
341 next_state->dma[NEXTDMA_ENRX].limit = val; in next_dma_write()
346 next_state->dma[NEXTDMA_SCSI].csr |= DMA_DEV2M; in next_dma_write()
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/qemu/hw/microblaze/
H A Dpetalogix_ml605_mmu.c74 DeviceState *dev, *dma, *eth0; in petalogix_ml605_init() local
139 dma = qdev_new("xlnx.axi-dma"); in petalogix_ml605_init()
143 object_property_add_child(qdev_get_machine(), "xilinx-dma", OBJECT(dma)); in petalogix_ml605_init()
145 ds = object_property_get_link(OBJECT(dma), in petalogix_ml605_init()
147 cs = object_property_get_link(OBJECT(dma), in petalogix_ml605_init()
164 qdev_prop_set_uint32(dma, "freqhz", 100 * 1000000); in petalogix_ml605_init()
165 object_property_set_link(OBJECT(dma), "axistream-connected", ds, in petalogix_ml605_init()
167 object_property_set_link(OBJECT(dma), "axistream-control-connected", cs, in petalogix_ml605_init()
169 sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal); in petalogix_ml605_init()
170 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, AXIDMA_BASEADDR); in petalogix_ml605_init()
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/qemu/include/hw/arm/
H A Dsoc_dma.h45 struct soc_dma_s *dma; member
97 void soc_dma_port_add_fifo(struct soc_dma_s *dma, hwaddr virt_base,
99 void soc_dma_port_add_mem(struct soc_dma_s *dma, uint8_t *phys_base,
102 static inline void soc_dma_port_add_fifo_in(struct soc_dma_s *dma, in soc_dma_port_add_fifo_in() argument
105 return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 0); in soc_dma_port_add_fifo_in()
108 static inline void soc_dma_port_add_fifo_out(struct soc_dma_s *dma, in soc_dma_port_add_fifo_out() argument
111 return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 1); in soc_dma_port_add_fifo_out()
/qemu/hw/ide/
H A Dpci.c198 static void bmdma_start_dma(const IDEDMA *dma, IDEState *s, in bmdma_start_dma() argument
201 BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma); in bmdma_start_dma()
221 static int32_t bmdma_prepare_buf(const IDEDMA *dma, int32_t limit) in bmdma_prepare_buf() argument
223 BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma); in bmdma_prepare_buf()
273 static int bmdma_rw_buf(const IDEDMA *dma, bool is_write) in bmdma_rw_buf() argument
275 BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma); in bmdma_rw_buf()
322 static void bmdma_set_inactive(const IDEDMA *dma, bool more) in bmdma_set_inactive() argument
324 BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma); in bmdma_set_inactive()
334 static void bmdma_restart_dma(const IDEDMA *dma) in bmdma_restart_dma() argument
336 BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma); in bmdma_restart_dma()
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H A Dmacio.c117 s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, offset, 0x1, in pmac_ide_atapi_transfer_cb()
182 s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, offset, 0x1, in pmac_ide_transfer_cb()
186 s->bus->dma->aiocb = dma_blk_write(s->blk, &s->sg, offset, 0x1, in pmac_ide_transfer_cb()
190 s->bus->dma->aiocb = dma_blk_io(&s->sg, offset, 0x1, ide_issue_trim, s, in pmac_ide_transfer_cb()
249 if (s->bus->dma->aiocb) { in pmac_ide_flush()
374 static int ide_nop_int(const IDEDMA *dma, bool is_write) in ide_nop_int() argument
379 static int32_t ide_nop_int32(const IDEDMA *dma, int32_t l) in ide_nop_int32() argument
384 static void ide_dbdma_start(const IDEDMA *dma, IDEState *s, in ide_dbdma_start() argument
387 MACIOIDEState *m = container_of(dma, MACIOIDEState, dma); in ide_dbdma_start()
420 s->dma.ops = &dbdma_ops; in macio_ide_realizefn()
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H A Dcore.c577 if (!s->bus->dma->ops->pio_transfer) { in ide_transfer_start_norecurse()
581 s->bus->dma->ops->pio_transfer(s->bus->dma); in ide_transfer_start_norecurse()
595 if (s->bus->dma->ops->cmd_done) { in ide_cmd_done()
596 s->bus->dma->ops->cmd_done(s->bus->dma); in ide_cmd_done()
755 if (s->bus->dma->aiocb) { in ide_cancel_dma_sync()
758 assert(s->bus->dma->aiocb == NULL); in ide_cancel_dma_sync()
832 if (s->bus->dma->ops->commit_buf) { in dma_buf_commit()
833 s->bus->dma->ops->commit_buf(s->bus->dma, tx_bytes); in dma_buf_commit()
841 s->bus->dma->aiocb = NULL; in ide_set_inactive()
843 if (s->bus->dma->ops->set_inactive) { in ide_set_inactive()
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H A Dahci.c44 static int ahci_dma_prepare_buf(const IDEDMA *dma, int32_t limit);
1371 static void ahci_pio_transfer(const IDEDMA *dma) in ahci_pio_transfer() argument
1373 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); in ahci_pio_transfer()
1401 if (ahci_dma_prepare_buf(dma, size)) { in ahci_pio_transfer()
1432 static void ahci_start_dma(const IDEDMA *dma, IDEState *s, in ahci_start_dma() argument
1435 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); in ahci_start_dma()
1441 static void ahci_restart_dma(const IDEDMA *dma) in ahci_restart_dma() argument
1450 static void ahci_restart(const IDEDMA *dma) in ahci_restart() argument
1452 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); in ahci_restart()
1467 static int32_t ahci_dma_prepare_buf(const IDEDMA *dma, int32_t limit) in ahci_dma_prepare_buf() argument
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/qemu/hw/nvram/
H A Dfw_cfg.c337 FWCfgDmaAccess dma; in fw_cfg_dma_transfer() local
348 &dma, sizeof(dma), MEMTXATTRS_UNSPECIFIED)) { in fw_cfg_dma_transfer()
354 dma.address = be64_to_cpu(dma.address); in fw_cfg_dma_transfer()
355 dma.length = be32_to_cpu(dma.length); in fw_cfg_dma_transfer()
356 dma.control = be32_to_cpu(dma.control); in fw_cfg_dma_transfer()
358 if (dma.control & FW_CFG_DMA_CTL_SELECT) { in fw_cfg_dma_transfer()
359 fw_cfg_select(s, dma.control >> 16); in fw_cfg_dma_transfer()
366 if (dma.control & FW_CFG_DMA_CTL_READ) { in fw_cfg_dma_transfer()
369 } else if (dma.control & FW_CFG_DMA_CTL_WRITE) { in fw_cfg_dma_transfer()
372 } else if (dma.control & FW_CFG_DMA_CTL_SKIP) { in fw_cfg_dma_transfer()
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/qemu/hw/block/
H A Dfdc-isa.c62 uint32_t dma; member
101 fdctrl->dma_chann = isa->dma; in isabus_fdc_realize()
104 fdctrl->dma = isa_bus_get_dma(bus, isa->dma); in isabus_fdc_realize()
105 if (!fdctrl->dma) { in isabus_fdc_realize()
109 k = ISADMA_GET_CLASS(fdctrl->dma); in isabus_fdc_realize()
110 k->register_channel(fdctrl->dma, fdctrl->dma_chann, in isabus_fdc_realize()
256 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, isa->dma)); in build_fdc_aml()
289 DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2),
/qemu/hw/arm/
H A Dbcm2838_peripherals.c117 sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->dma), n, in bcm2838_peripherals_realize()
130 sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->dma), 7, in bcm2838_peripherals_realize()
132 sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->dma), 8, in bcm2838_peripherals_realize()
147 sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->dma), 9, in bcm2838_peripherals_realize()
149 sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->dma), 10, in bcm2838_peripherals_realize()
159 sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->dma), n, in bcm2838_peripherals_realize()
170 sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->dma), 15, in bcm2838_peripherals_realize()
/qemu/hw/audio/
H A Dsb16.c61 uint32_t dma; member
180 int dma = s->use_hdma ? s->hdma : s->dma; in control() local
185 ldebug ("hold %d high %d dma %d\n", hold, s->use_hdma, dma); in control()
188 k->hold_DREQ(isa_dma, dma); in control()
192 k->release_DREQ(isa_dma, dma); in control()
1130 int dma, hdma; in mixer_write_datab() local
1132 dma = ctz32 (val & 0xf); in mixer_write_datab()
1134 if (dma != s->dma || hdma != s->hdma) { in mixer_write_datab()
1136 " %d(%d), 16bit %d(%d) (val=%#x)\n", dma, s->dma, in mixer_write_datab()
1140 s->dma = dma; in mixer_write_datab()
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H A Dcs4231a.c78 uint32_t dma; member
341 k->hold_DREQ(s->isa_dma, s->dma); in cs_reset_voices()
349 k->release_DREQ(s->isa_dma, s->dma); in cs_reset_voices()
358 k->release_DREQ(s->isa_dma, s->dma); in cs_reset_voices()
467 k->release_DREQ(s->isa_dma, s->dma); in cs_write()
616 k->release_DREQ(s->isa_dma, s->dma); in cs4231a_pre_load()
675 s->isa_dma = isa_bus_get_dma(bus, s->dma); in cs4231a_realizefn()
691 k->register_channel(s->isa_dma, s->dma, cs_dma_read, s); in cs4231a_realizefn()
700 DEFINE_PROP_UINT32 ("dma", CSState, dma, 3),
/qemu/hw/isa/
H A Disa-bus.c110 assert(!bus->dma[0] && !bus->dma[1]); in isa_bus_dma()
111 bus->dma[0] = dma8; in isa_bus_dma()
112 bus->dma[1] = dma16; in isa_bus_dma()
118 return bus->dma[nchan > 3 ? 1 : 0]; in isa_bus_get_dma()
/qemu/include/hw/mips/
H A Dmips.h17 void rc4030_dma_read(void *dma, uint8_t *buf, int len);
18 void rc4030_dma_write(void *dma, uint8_t *buf, int len);
/qemu/tests/qemu-iotests/
H A D172.out14 dma = 2 (0x2)
43 dma = 2 (0x2)
79 dma = 2 (0x2)
133 dma = 2 (0x2)
188 dma = 2 (0x2)
231 dma = 2 (0x2)
267 dma = 2 (0x2)
321 dma = 2 (0x2)
379 dma = 2 (0x2)
415 dma = 2 (0x2)
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/qemu/hw/uefi/
H A Dvar-service-core.c64 hwaddr dma; in uefi_vars_cmd_mm() local
69 dma = uv->buf_addr_lo | ((hwaddr)uv->buf_addr_hi << 32); in uefi_vars_cmd_mm()
78 dma_memory_read(&address_space_memory, dma, in uefi_vars_cmd_mm()
94 dma_memory_read(&address_space_memory, dma + sizeof(*mhdr), in uefi_vars_cmd_mm()
132 dma_memory_write(&address_space_memory, dma, in uefi_vars_cmd_mm()
/qemu/hw/i2c/
H A Domap_i2c.c45 uint16_t dma; member
64 if ((s->dma >> 15) & 1) /* RDMA_EN */ in omap_i2c_interrupts_update()
66 if ((s->dma >> 7) & 1) /* XDMA_EN */ in omap_i2c_interrupts_update()
144 s->dma = 0; in omap_i2c_reset()
192 return s->dma; in omap_i2c_read()
292 s->dma = value & 0x8080; in omap_i2c_write()
/qemu/hw/scsi/
H A Desp.c148 if (s->dma) { in esp_update_drq()
365 if (s->dma && !s->dma_enabled) { in handle_satn()
376 if (s->dma) { in handle_satn()
385 if (s->dma && !s->dma_enabled) { in handle_s_without_atn()
397 if (s->dma) { in handle_s_without_atn()
406 if (s->dma && !s->dma_enabled) { in handle_satn_stop()
418 if (s->dma) { in handle_satn_stop()
427 if (s->dma) { in handle_pad()
438 if (s->dma) { in write_response()
943 if (s->dma || to_device) { in esp_command_complete()
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