1 /*
2 * QEMU IDE Emulation: MacIO support.
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 #include "qemu/osdep.h"
27 #include "hw/irq.h"
28 #include "hw/ppc/mac_dbdma.h"
29 #include "hw/qdev-properties.h"
30 #include "migration/vmstate.h"
31 #include "qemu/module.h"
32 #include "hw/misc/macio/macio.h"
33 #include "system/block-backend.h"
34 #include "system/dma.h"
35
36 #include "ide-internal.h"
37
38 /* debug MACIO */
39 // #define DEBUG_MACIO
40
41 #ifdef DEBUG_MACIO
42 static const int debug_macio = 1;
43 #else
44 static const int debug_macio = 0;
45 #endif
46
47 #define MACIO_DPRINTF(fmt, ...) do { \
48 if (debug_macio) { \
49 printf(fmt , ## __VA_ARGS__); \
50 } \
51 } while (0)
52
53
54 /***********************************************************/
55 /* MacIO based PowerPC IDE */
56
57 #define MACIO_PAGE_SIZE 4096
58
pmac_ide_atapi_transfer_cb(void * opaque,int ret)59 static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
60 {
61 DBDMA_io *io = opaque;
62 MACIOIDEState *m = io->opaque;
63 IDEState *s = ide_bus_active_if(&m->bus);
64 int64_t offset;
65
66 MACIO_DPRINTF("pmac_ide_atapi_transfer_cb\n");
67
68 if (ret < 0) {
69 MACIO_DPRINTF("DMA error: %d\n", ret);
70 qemu_sglist_destroy(&s->sg);
71 ide_atapi_io_error(s, ret);
72 goto done;
73 }
74
75 if (!m->dma_active) {
76 MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
77 s->nsector, io->len, s->status);
78 /* data not ready yet, wait for the channel to get restarted */
79 io->processing = false;
80 return;
81 }
82
83 if (s->io_buffer_size <= 0) {
84 MACIO_DPRINTF("End of IDE transfer\n");
85 qemu_sglist_destroy(&s->sg);
86 ide_atapi_cmd_ok(s);
87 m->dma_active = false;
88 goto done;
89 }
90
91 if (io->len == 0) {
92 MACIO_DPRINTF("End of DMA transfer\n");
93 goto done;
94 }
95
96 if (s->lba == -1) {
97 /* Non-block ATAPI transfer - just copy to RAM */
98 s->io_buffer_size = MIN(s->io_buffer_size, io->len);
99 dma_memory_write(&address_space_memory, io->addr, s->io_buffer,
100 s->io_buffer_size, MEMTXATTRS_UNSPECIFIED);
101 io->len = 0;
102 ide_atapi_cmd_ok(s);
103 m->dma_active = false;
104 goto done;
105 }
106
107 /* Calculate current offset */
108 offset = ((int64_t)s->lba << 11) + s->io_buffer_index;
109
110 qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1,
111 &address_space_memory);
112 qemu_sglist_add(&s->sg, io->addr, io->len);
113 s->io_buffer_size -= io->len;
114 s->io_buffer_index += io->len;
115 io->len = 0;
116
117 s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, offset, 0x1,
118 pmac_ide_atapi_transfer_cb, io);
119 return;
120
121 done:
122 if (ret < 0) {
123 block_acct_failed(blk_get_stats(s->blk), &s->acct);
124 } else {
125 block_acct_done(blk_get_stats(s->blk), &s->acct);
126 }
127
128 ide_set_inactive(s, false);
129 io->dma_end(opaque);
130 }
131
pmac_ide_transfer_cb(void * opaque,int ret)132 static void pmac_ide_transfer_cb(void *opaque, int ret)
133 {
134 DBDMA_io *io = opaque;
135 MACIOIDEState *m = io->opaque;
136 IDEState *s = ide_bus_active_if(&m->bus);
137 int64_t offset;
138
139 MACIO_DPRINTF("pmac_ide_transfer_cb\n");
140
141 if (ret < 0) {
142 MACIO_DPRINTF("DMA error: %d\n", ret);
143 qemu_sglist_destroy(&s->sg);
144 ide_dma_error(s);
145 goto done;
146 }
147
148 if (!m->dma_active) {
149 MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
150 s->nsector, io->len, s->status);
151 /* data not ready yet, wait for the channel to get restarted */
152 io->processing = false;
153 return;
154 }
155
156 if (s->io_buffer_size <= 0) {
157 MACIO_DPRINTF("End of IDE transfer\n");
158 qemu_sglist_destroy(&s->sg);
159 s->status = READY_STAT | SEEK_STAT;
160 ide_bus_set_irq(s->bus);
161 m->dma_active = false;
162 goto done;
163 }
164
165 if (io->len == 0) {
166 MACIO_DPRINTF("End of DMA transfer\n");
167 goto done;
168 }
169
170 /* Calculate number of sectors */
171 offset = (ide_get_sector(s) << 9) + s->io_buffer_index;
172
173 qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1,
174 &address_space_memory);
175 qemu_sglist_add(&s->sg, io->addr, io->len);
176 s->io_buffer_size -= io->len;
177 s->io_buffer_index += io->len;
178 io->len = 0;
179
180 switch (s->dma_cmd) {
181 case IDE_DMA_READ:
182 s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, offset, 0x1,
183 pmac_ide_atapi_transfer_cb, io);
184 break;
185 case IDE_DMA_WRITE:
186 s->bus->dma->aiocb = dma_blk_write(s->blk, &s->sg, offset, 0x1,
187 pmac_ide_transfer_cb, io);
188 break;
189 case IDE_DMA_TRIM:
190 s->bus->dma->aiocb = dma_blk_io(&s->sg, offset, 0x1, ide_issue_trim, s,
191 pmac_ide_transfer_cb, io,
192 DMA_DIRECTION_TO_DEVICE);
193 break;
194 default:
195 abort();
196 }
197
198 return;
199
200 done:
201 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
202 if (ret < 0) {
203 block_acct_failed(blk_get_stats(s->blk), &s->acct);
204 } else {
205 block_acct_done(blk_get_stats(s->blk), &s->acct);
206 }
207 }
208
209 ide_set_inactive(s, false);
210 io->dma_end(opaque);
211 }
212
pmac_ide_transfer(DBDMA_io * io)213 static void pmac_ide_transfer(DBDMA_io *io)
214 {
215 MACIOIDEState *m = io->opaque;
216 IDEState *s = ide_bus_active_if(&m->bus);
217
218 MACIO_DPRINTF("\n");
219
220 if (s->drive_kind == IDE_CD) {
221 block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
222 BLOCK_ACCT_READ);
223
224 pmac_ide_atapi_transfer_cb(io, 0);
225 return;
226 }
227
228 switch (s->dma_cmd) {
229 case IDE_DMA_READ:
230 block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
231 BLOCK_ACCT_READ);
232 break;
233 case IDE_DMA_WRITE:
234 block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
235 BLOCK_ACCT_WRITE);
236 break;
237 default:
238 break;
239 }
240
241 pmac_ide_transfer_cb(io, 0);
242 }
243
pmac_ide_flush(DBDMA_io * io)244 static void pmac_ide_flush(DBDMA_io *io)
245 {
246 MACIOIDEState *m = io->opaque;
247 IDEState *s = ide_bus_active_if(&m->bus);
248
249 if (s->bus->dma->aiocb) {
250 blk_drain(s->blk);
251 }
252 }
253
254 /* PowerMac IDE memory IO */
pmac_ide_read(void * opaque,hwaddr addr,unsigned size)255 static uint64_t pmac_ide_read(void *opaque, hwaddr addr, unsigned size)
256 {
257 MACIOIDEState *d = opaque;
258 uint64_t retval = 0xffffffff;
259 int reg = addr >> 4;
260
261 switch (reg) {
262 case 0x0:
263 if (size == 1) {
264 retval = ide_data_readw(&d->bus, 0) & 0xFF;
265 } else if (size == 2) {
266 retval = ide_data_readw(&d->bus, 0);
267 } else if (size == 4) {
268 retval = ide_data_readl(&d->bus, 0);
269 }
270 break;
271 case 0x1 ... 0x7:
272 if (size == 1) {
273 retval = ide_ioport_read(&d->bus, reg);
274 }
275 break;
276 case 0x8:
277 case 0x16:
278 if (size == 1) {
279 retval = ide_status_read(&d->bus, 0);
280 }
281 break;
282 case 0x20:
283 if (size == 4) {
284 retval = d->timing_reg;
285 }
286 break;
287 case 0x30:
288 /* This is an interrupt state register that only exists
289 * in the KeyLargo and later variants. Bit 0x8000_0000
290 * latches the DMA interrupt and has to be written to
291 * clear. Bit 0x4000_0000 is an image of the disk
292 * interrupt. MacOS X relies on this and will hang if
293 * we don't provide at least the disk interrupt
294 */
295 if (size == 4) {
296 retval = d->irq_reg;
297 }
298 break;
299 }
300
301 return retval;
302 }
303
304
pmac_ide_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)305 static void pmac_ide_write(void *opaque, hwaddr addr, uint64_t val,
306 unsigned size)
307 {
308 MACIOIDEState *d = opaque;
309 int reg = addr >> 4;
310
311 switch (reg) {
312 case 0x0:
313 if (size == 2) {
314 ide_data_writew(&d->bus, 0, val);
315 } else if (size == 4) {
316 ide_data_writel(&d->bus, 0, val);
317 }
318 break;
319 case 0x1 ... 0x7:
320 if (size == 1) {
321 ide_ioport_write(&d->bus, reg, val);
322 }
323 break;
324 case 0x8:
325 case 0x16:
326 if (size == 1) {
327 ide_ctrl_write(&d->bus, 0, val);
328 }
329 break;
330 case 0x20:
331 if (size == 4) {
332 d->timing_reg = val;
333 }
334 break;
335 case 0x30:
336 if (size == 4) {
337 if (val & 0x80000000u) {
338 d->irq_reg &= 0x7fffffff;
339 }
340 }
341 break;
342 }
343 }
344
345 static const MemoryRegionOps pmac_ide_ops = {
346 .read = pmac_ide_read,
347 .write = pmac_ide_write,
348 .valid.min_access_size = 1,
349 .valid.max_access_size = 4,
350 .endianness = DEVICE_LITTLE_ENDIAN,
351 };
352
353 static const VMStateDescription vmstate_pmac = {
354 .name = "ide",
355 .version_id = 5,
356 .minimum_version_id = 0,
357 .fields = (const VMStateField[]) {
358 VMSTATE_IDE_BUS(bus, MACIOIDEState),
359 VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState),
360 VMSTATE_BOOL(dma_active, MACIOIDEState),
361 VMSTATE_UINT32(timing_reg, MACIOIDEState),
362 VMSTATE_UINT32(irq_reg, MACIOIDEState),
363 VMSTATE_END_OF_LIST()
364 }
365 };
366
macio_ide_reset(DeviceState * dev)367 static void macio_ide_reset(DeviceState *dev)
368 {
369 MACIOIDEState *d = MACIO_IDE(dev);
370
371 ide_bus_reset(&d->bus);
372 }
373
ide_nop_int(const IDEDMA * dma,bool is_write)374 static int ide_nop_int(const IDEDMA *dma, bool is_write)
375 {
376 return 0;
377 }
378
ide_nop_int32(const IDEDMA * dma,int32_t l)379 static int32_t ide_nop_int32(const IDEDMA *dma, int32_t l)
380 {
381 return 0;
382 }
383
ide_dbdma_start(const IDEDMA * dma,IDEState * s,BlockCompletionFunc * cb)384 static void ide_dbdma_start(const IDEDMA *dma, IDEState *s,
385 BlockCompletionFunc *cb)
386 {
387 MACIOIDEState *m = container_of(dma, MACIOIDEState, dma);
388
389 s->io_buffer_index = 0;
390 if (s->drive_kind == IDE_CD) {
391 s->io_buffer_size = s->packet_transfer_size;
392 } else {
393 s->io_buffer_size = s->nsector * BDRV_SECTOR_SIZE;
394 }
395
396 MACIO_DPRINTF("\n\n------------ IDE transfer\n");
397 MACIO_DPRINTF("buffer_size: %x buffer_index: %x\n",
398 s->io_buffer_size, s->io_buffer_index);
399 MACIO_DPRINTF("lba: %x size: %x\n", s->lba, s->io_buffer_size);
400 MACIO_DPRINTF("-------------------------\n");
401
402 m->dma_active = true;
403 DBDMA_kick(m->dbdma);
404 }
405
406 static const IDEDMAOps dbdma_ops = {
407 .start_dma = ide_dbdma_start,
408 .prepare_buf = ide_nop_int32,
409 .rw_buf = ide_nop_int,
410 };
411
macio_ide_realizefn(DeviceState * dev,Error ** errp)412 static void macio_ide_realizefn(DeviceState *dev, Error **errp)
413 {
414 MACIOIDEState *s = MACIO_IDE(dev);
415
416 ide_bus_init_output_irq(&s->bus,
417 qdev_get_gpio_in(dev, MACIO_IDE_PMAC_IDE_IRQ));
418
419 /* Register DMA callbacks */
420 s->dma.ops = &dbdma_ops;
421 s->bus.dma = &s->dma;
422 }
423
pmac_ide_irq(void * opaque,int n,int level)424 static void pmac_ide_irq(void *opaque, int n, int level)
425 {
426 MACIOIDEState *s = opaque;
427 uint32_t mask = 0x80000000u >> n;
428
429 /* We need to reflect the IRQ state in the irq register */
430 if (level) {
431 s->irq_reg |= mask;
432 } else {
433 s->irq_reg &= ~mask;
434 }
435
436 if (n) {
437 qemu_set_irq(s->real_ide_irq, level);
438 } else {
439 qemu_set_irq(s->real_dma_irq, level);
440 }
441 }
442
macio_ide_initfn(Object * obj)443 static void macio_ide_initfn(Object *obj)
444 {
445 SysBusDevice *d = SYS_BUS_DEVICE(obj);
446 MACIOIDEState *s = MACIO_IDE(obj);
447
448 ide_bus_init(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
449 memory_region_init_io(&s->mem, obj, &pmac_ide_ops, s, "pmac-ide", 0x1000);
450 sysbus_init_mmio(d, &s->mem);
451 sysbus_init_irq(d, &s->real_ide_irq);
452 sysbus_init_irq(d, &s->real_dma_irq);
453
454 qdev_init_gpio_in(DEVICE(obj), pmac_ide_irq, MACIO_IDE_PMAC_NIRQS);
455
456 object_property_add_link(obj, "dbdma", TYPE_MAC_DBDMA,
457 (Object **) &s->dbdma,
458 qdev_prop_allow_set_link_before_realize, 0);
459 }
460
461 static const Property macio_ide_properties[] = {
462 DEFINE_PROP_UINT32("channel", MACIOIDEState, channel, 0),
463 DEFINE_PROP_UINT32("addr", MACIOIDEState, addr, -1),
464 };
465
macio_ide_class_init(ObjectClass * oc,const void * data)466 static void macio_ide_class_init(ObjectClass *oc, const void *data)
467 {
468 DeviceClass *dc = DEVICE_CLASS(oc);
469
470 dc->realize = macio_ide_realizefn;
471 device_class_set_legacy_reset(dc, macio_ide_reset);
472 device_class_set_props(dc, macio_ide_properties);
473 dc->vmsd = &vmstate_pmac;
474 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
475 }
476
477 static const TypeInfo macio_ide_type_info = {
478 .name = TYPE_MACIO_IDE,
479 .parent = TYPE_SYS_BUS_DEVICE,
480 .instance_size = sizeof(MACIOIDEState),
481 .instance_init = macio_ide_initfn,
482 .class_init = macio_ide_class_init,
483 };
484
macio_ide_register_types(void)485 static void macio_ide_register_types(void)
486 {
487 type_register_static(&macio_ide_type_info);
488 }
489
490 /* hd_table must contain 2 block drivers */
macio_ide_init_drives(MACIOIDEState * s,DriveInfo ** hd_table)491 void macio_ide_init_drives(MACIOIDEState *s, DriveInfo **hd_table)
492 {
493 int i;
494
495 for (i = 0; i < 2; i++) {
496 if (hd_table[i]) {
497 ide_bus_create_drive(&s->bus, i, hd_table[i]);
498 }
499 }
500 }
501
macio_ide_register_dma(MACIOIDEState * s)502 void macio_ide_register_dma(MACIOIDEState *s)
503 {
504 DBDMA_register_channel(s->dbdma, s->channel,
505 qdev_get_gpio_in(DEVICE(s), MACIO_IDE_PMAC_DMA_IRQ),
506 pmac_ide_transfer, pmac_ide_flush, s);
507 }
508
509 type_init(macio_ide_register_types)
510