74     } dma;  member
145     if (!(edu->dma.cmd & EDU_DMA_RUN)) {  in edu_dma_timer()
149     if (EDU_DMA_DIR(edu->dma.cmd) == EDU_DMA_FROM_PCI) {  in edu_dma_timer()
150         uint64_t dst = edu->dma.dst;  in edu_dma_timer()
151         edu_check_range(dst, edu->dma.cnt, DMA_START, DMA_SIZE);  in edu_dma_timer()
153         pci_dma_read(&edu->pdev, edu_clamp_addr(edu, edu->dma.src),  in edu_dma_timer()
154                 edu->dma_buf + dst, edu->dma.cnt);  in edu_dma_timer()
156         uint64_t src = edu->dma.src;  in edu_dma_timer()
157         edu_check_range(src, edu->dma.cnt, DMA_START, DMA_SIZE);  in edu_dma_timer()
159         pci_dma_write(&edu->pdev, edu_clamp_addr(edu, edu->dma.dst),  in edu_dma_timer()
160                 edu->dma_buf + src, edu->dma.cnt);  in edu_dma_timer()
163     edu->dma.cmd &= ~EDU_DMA_RUN;  in edu_dma_timer()
164     if (edu->dma.cmd & EDU_DMA_IRQ) {  in edu_dma_timer()
173 static void dma_rw(EduState *edu, bool write, dma_addr_t *val, dma_addr_t *dma,  in dma_rw()  argument
176     if (write && (edu->dma.cmd & EDU_DMA_RUN)) {  in dma_rw()
181         *dma = *val;  in dma_rw()
183         *val = *dma;  in dma_rw()
223         dma_rw(edu, false, &val, &edu->dma.src, false);  in edu_mmio_read()
226         dma_rw(edu, false, &val, &edu->dma.dst, false);  in edu_mmio_read()
229         dma_rw(edu, false, &val, &edu->dma.cnt, false);  in edu_mmio_read()
232         dma_rw(edu, false, &val, &edu->dma.cmd, false);  in edu_mmio_read()
285         dma_rw(edu, true, &val, &edu->dma.src, false);  in edu_mmio_write()
288         dma_rw(edu, true, &val, &edu->dma.dst, false);  in edu_mmio_write()
291         dma_rw(edu, true, &val, &edu->dma.cnt, false);  in edu_mmio_write()
297         dma_rw(edu, true, &val, &edu->dma.cmd, true);  in edu_mmio_write()