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/linux-3.3/arch/blackfin/mach-bf518/include/mach/
DdefBF516.h2 * Copyright 2008-2009 Analog Devices Inc.
4 * Licensed under the ADI BSD license or the GPL-2 (or later)
13 /* The following are the #defines needed by ADSP-BF516 that are not in the common header */
14 /* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
19 #define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register …
20 #define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register…
26 #define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register …
27 #define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register …
28 #define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register …
29 #define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register …
[all …]
/linux-3.3/arch/blackfin/mach-bf527/include/mach/
DdefBF527.h2 * Copyright 2007-2010 Analog Devices Inc.
4 * Licensed under the ADI BSD license or the GPL-2 (or later)
13 /* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
18 #define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register …
19 #define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register…
25 #define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register …
26 #define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register …
27 #define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register …
28 #define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register …
29 #define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register …
[all …]
DdefBF525.h2 * Copyright 2007-2010 Analog Devices Inc.
4 * Licensed under the ADI BSD license or the GPL-2 (or later)
17 #define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx …
18 #define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to …
31 #define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint …
32 …844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
33 …844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
34 #define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint …
35 #define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpo…
36 … /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
[all …]
/linux-3.3/arch/blackfin/mach-bf537/include/mach/
DdefBF537.h2 * Copyright 2005-2010 Analog Devices Inc.
4 * Licensed under the ADI BSD license or the GPL-2 (or later)
17 /* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
21 #define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
22 #define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
28 #define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register …
29 #define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register …
30 #define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register …
31 #define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register …
32 #define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register …
[all …]
/linux-3.3/drivers/net/ethernet/brocade/bna/
Dbna_tx_rx.c14 * Copyright (c) 2005-2011 Brocade Communications Systems, Inc.
27 ib->coalescing_timeo = coalescing_timeo; in bna_ib_coalescing_timeo_set()
28 ib->door_bell.doorbell_ack = BNA_DOORBELL_IB_INT_ACK( in bna_ib_coalescing_timeo_set()
29 (u32)ib->coalescing_timeo, 0); in bna_ib_coalescing_timeo_set()
38 (rxf)->vlan_pending_bitmask = (u8)BFI_VLAN_BMASK_ALL; \
39 (rxf)->vlan_strip_pending = true; \
44 if ((rxf)->rss_status == BNA_STATUS_T_ENABLED) \
45 (rxf)->rss_pending = (BNA_RSS_F_RIT_PENDING | \
88 if (rxf->flags & BNA_RXF_F_PAUSED) { in bna_rxf_sm_stopped()
100 /* No-op */ in bna_rxf_sm_stopped()
[all …]
Dbfa_defs_cna.h14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
29 u64 tx_frames; /*!< Tx frames */
30 u64 tx_words; /*!< Tx words */
31 u64 tx_lip; /*!< Tx LIP */
32 u64 tx_nos; /*!< Tx NOS */
33 u64 tx_ols; /*!< Tx OLS */
34 u64 tx_lr; /*!< Tx LR */
35 u64 tx_lrr; /*!< Tx LRR */
36 u64 rx_frames; /*!< Rx frames */
37 u64 rx_words; /*!< Rx words */
[all …]
/linux-3.3/arch/m68k/include/asm/
Dm68360_pram.h40 unsigned short tsatrx[32]; /* Time Slot Assignment Table Rx */
41 unsigned short tsattx[32]; /* Time Slot Assignment Table Tx */
50 unsigned short tbase; /* Tx Buffer Descriptors Base Address */
52 unsigned long tstate; /* Tx Internal State */
53 unsigned long txintr; /* Tx Internal Data Pointer */
54 unsigned short tbptr; /* Tx Buffer Descriptor Pointer */
55 unsigned short txcntr; /* Tx Internal Byte Count */
56 unsigned long tupack; /* (Tx Temp) */
61 unsigned short rbase; /* Rx Buffer Descriptors Base Address */
63 unsigned long rstate; /* Rx Internal State */
[all …]
/linux-3.3/drivers/usb/musb/
Dcppi_dma.c2 * Copyright (C) 2005-2006 by Texas Instruments
5 * For now it's DaVinci-only, but CPPI isn't specific to DaVinci or USB.
18 /* CPPI DMA status 7-mar-2006:
20 * - See musb_{host,gadget}.c for more info
22 * - Correct RX DMA generally forces the engine into irq-per-packet mode,
23 * which can easily saturate the CPU under non-mass-storage loads.
25 * NOTES 24-aug-2006 (2.6.18-rc4):
27 * - peripheral RXDMA wedged in a test with packets of length 512/512/1.
30 * and RX DMA0: 4 left, 80000000 8feff880, 8feff860 8feff860; 8f321401
31 * 004001ff 00000001 .. 8feff860) Host was just getting NAKed on tx
[all …]
/linux-3.3/arch/blackfin/include/asm/
Dbfin_can.h2 * bfin_can.h - interface to Blackfin CANs
4 * Copyright 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
37 /* data[0,2,4,6] -> data{0,1,2,3} while data[1,3,5,7] is padding */
112 #define ABO 0x0004 /* Auto-Bus On Enable */
113 #define TXPRIO 0x0008 /* TX Priority (Priority/Mailbox*) */
114 #define WBA 0x0010 /* Wake-Up On CAN Bus Activity Enable */
120 #define WT 0x0001 /* TX Warning Flag */
121 #define WR 0x0002 /* RX Warning Flag */
132 #define BRP 0x03FF /* Bit-Rate Pre-Scaler */
[all …]
Dbfin_sport.h2 * bfin_sport.h - interface to Blackfin SPORTs
4 * Copyright 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
17 /* Data format, normal, a-law or u-law */
50 unsigned int data_format:2; /* Normal, u-law or a-law */
52 int word_len; /* How length of the word in bits, 3-32 bits */
114 __ret = __mmrs->rx32; \
123 #define TSPEN 0x0001 /* TX enable */
124 #define ITCLK 0x0002 /* Internal TX Clock Select */
125 #define TDTYPE 0x000C /* TX Data Formatting Select */
[all …]
/linux-3.3/drivers/net/wireless/b43/
Dradio_2055.h14 #define B2055_C1_SP_RXGC1 0x07 /* SP RX GC1 Core 1 */
15 #define B2055_C1_SP_RXGC2 0x08 /* SP RX GC2 Core 1 */
16 #define B2055_C2_SP_RXGC1 0x09 /* SP RX GC1 Core 2 */
17 #define B2055_C2_SP_RXGC2 0x0A /* SP RX GC2 Core 2 */
20 #define B2055_C1_SP_TXGC1 0x0D /* SP TX GC1 Core 1 */
21 #define B2055_C1_SP_TXGC2 0x0E /* SP TX GC2 Core 1 */
22 #define B2055_C2_SP_TXGC1 0x0F /* SP TX GC1 Core 2 */
23 #define B2055_C2_SP_TXGC2 0x10 /* SP TX GC2 Core 2 */
29 #define B2055_C1_PD_TX 0x16 /* PD Core 1 TX */
33 #define B2055_C2_PD_TX 0x1A /* PD Core 2 TX */
[all …]
/linux-3.3/drivers/staging/media/lirc/
Dlirc_zilog.c4 * Copyright (c) 2000 Gerd Knorr <kraxel@goldbach.in-berlin.de>
10 * modified for Asus TV-Box and Creative/VisionTek BreakOut-Box by
16 * modified for Hauppauge PVR-150 IR TX device by
18 * changed name from lirc_pvr150 to lirc_zilog, works on more than pvr-150
38 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
70 /* RX device */
74 /* RX polling thread data */
77 /* RX read data */
86 /* TX device */
90 /* TX additional actions needed */
[all …]
/linux-3.3/drivers/net/ethernet/pasemi/
Dpasemi_mac_ethtool.c2 * Copyright (C) 2006-2008 PA Semi, Inc
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
32 { "rx-drops" },
33 { "rx-bytes" },
34 { "rx-packets" },
35 { "rx-broadcast-packets" },
36 { "rx-multicast-packets" },
37 { "rx-crc-errors" },
38 { "rx-undersize-errors" },
39 { "rx-oversize-errors" },
[all …]
/linux-3.3/drivers/net/ethernet/sun/
Dsunqe.h14 #define GLOB_MSIZE 0x0cUL /* Local-memory Size */
44 /* The following registers are for per-qe channel information/status. */
47 #define CREG_RXDS 0x08UL /* RX descriptor ring ptr */
48 #define CREG_TXDS 0x0cUL /* TX descriptor ring ptr */
49 #define CREG_RIMASK 0x10UL /* RX Interrupt Mask */
50 #define CREG_TIMASK 0x14UL /* TX Interrupt Mask */
53 #define CREG_RXWBUFPTR 0x20UL /* Local memory rx write ptr */
54 #define CREG_RXRBUFPTR 0x24UL /* Local memory rx read ptr */
55 #define CREG_TXWBUFPTR 0x28UL /* Local memory tx write ptr */
56 #define CREG_TXRBUFPTR 0x2cUL /* Local memory tx read ptr */
[all …]
Dsungem.h25 #define GREG_SEBSTATE_RXWON 0x00000004 /* RX won internal arbitration */
29 #define GREG_CFG_TXDMALIM 0x0000003e /* TX DMA grant limit */
30 #define GREG_CFG_RXDMALIM 0x000007c0 /* RX DMA grant limit */
33 #define GREG_CFG_ENBUG2FIX 0x00001000 /* Fix Rx hang after overflow */
38 * This auto-clearing does not occur when the alias at GREG_STAT2
44 #define GREG_STAT_TXINTME 0x00000001 /* TX INTME frame transferred */
45 #define GREG_STAT_TXALL 0x00000002 /* All TX frames transferred */
46 #define GREG_STAT_TXDONE 0x00000004 /* One TX frame transferred */
47 #define GREG_STAT_RXDONE 0x00000010 /* One RX frame arrived */
48 #define GREG_STAT_RXNOBUF 0x00000020 /* No free RX buffers available */
[all …]
/linux-3.3/drivers/tty/serial/
Dmsm_serial_hs.c4 * Copyright (c) 2007-2011, Code Aurora Forum. All rights reserved.
20 * RX wakeup.
21 * UART wakeup can be triggered by RX activity (using a wakeup GPIO on the
22 * UART RX pin). This should only be used if there is not a wakeup
23 * GPIO on the UART CTS, and the first RX byte is known (for example, with the
24 * Bluetooth Texas Instruments HCILL protocol), since the first RX byte will
46 #include <linux/dma-mapping.h>
205 /* Rx DMA request states */
219 MSM_HS_CLK_REQUEST_OFF, /* disable after TX and RX flushed */
234 * @tx_ready_int_en: ok to dma more tx?
[all …]
/linux-3.3/drivers/net/ethernet/stmicro/stmmac/
Dnorm_desc.c4 Copyright (C) 2007-2009 STMicroelectronics Ltd
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
34 if (unlikely(p->des01.tx.error_summary)) { in ndesc_get_tx_status()
35 if (unlikely(p->des01.tx.underflow_error)) { in ndesc_get_tx_status()
36 x->tx_underflow++; in ndesc_get_tx_status()
37 stats->tx_fifo_errors++; in ndesc_get_tx_status()
39 if (unlikely(p->des01.tx.no_carrier)) { in ndesc_get_tx_status()
40 x->tx_carrier++; in ndesc_get_tx_status()
41 stats->tx_carrier_errors++; in ndesc_get_tx_status()
43 if (unlikely(p->des01.tx.loss_carrier)) { in ndesc_get_tx_status()
[all …]
/linux-3.3/drivers/net/ethernet/intel/igb/
De1000_regs.h4 Copyright(c) 2007-2012 Intel Corporation.
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 #define E1000_CTRL 0x00000 /* Device Control - RW */
32 #define E1000_STATUS 0x00008 /* Device Status - RO */
33 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
34 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
35 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
36 #define E1000_MDIC 0x00020 /* MDI Control - RW */
[all …]
/linux-3.3/drivers/staging/iio/meter/
Dade7854-i2c.c6 * Licensed under the GPL-2 or later.
26 mutex_lock(&st->buf_lock); in ade7854_i2c_write_reg_8()
27 st->tx[0] = (reg_address >> 8) & 0xFF; in ade7854_i2c_write_reg_8()
28 st->tx[1] = reg_address & 0xFF; in ade7854_i2c_write_reg_8()
29 st->tx[2] = value; in ade7854_i2c_write_reg_8()
31 ret = i2c_master_send(st->i2c, st->tx, 3); in ade7854_i2c_write_reg_8()
32 mutex_unlock(&st->buf_lock); in ade7854_i2c_write_reg_8()
45 mutex_lock(&st->buf_lock); in ade7854_i2c_write_reg_16()
46 st->tx[0] = (reg_address >> 8) & 0xFF; in ade7854_i2c_write_reg_16()
47 st->tx[1] = reg_address & 0xFF; in ade7854_i2c_write_reg_16()
[all …]
/linux-3.3/sound/arm/
Daaci.h2 * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver
22 #define AACI_RXCR 0x000 /* 29 bits Control Rx FIFO */
23 #define AACI_TXCR 0x004 /* 17 bits Control Tx FIFO */
52 * TX/RX fifo control register (CR). P48
77 #define SR_RXTOFE (1 << 11) /* rx timeout fifo empty */
78 #define SR_TXTO (1 << 10) /* rx timeout fifo nonempty */
79 #define SR_TXU (1 << 9) /* tx underrun */
80 #define SR_RXO (1 << 8) /* rx overrun */
81 #define SR_TXB (1 << 7) /* tx busy */
82 #define SR_RXB (1 << 6) /* rx busy */
[all …]
/linux-3.3/drivers/net/ethernet/freescale/
Ducc_geth_ethtool.c10 * Need to re-open the interface manually after changing some parameters.
29 #include <linux/dma-mapping.h>
42 "tx-64-frames",
43 "tx-65-127-frames",
44 "tx-128-255-frames",
45 "rx-64-frames",
46 "rx-65-127-frames",
47 "rx-128-255-frames",
48 "tx-bytes-ok",
49 "tx-pause-frames",
[all …]
/linux-3.3/include/linux/
Dtipc_config.h4 * Copyright (c) 2003-2006, Ericsson AB
5 * Copyright (c) 2005-2007, 2010-2011, Wind River Systems
53 * back. (In the future multi-message replies may be supported.)
73 #define TIPC_CMD_NOOP 0x0000 /* tx none, rx none */
74 #define TIPC_CMD_GET_NODES 0x0001 /* tx net_addr, rx node_info(s) */
75 #define TIPC_CMD_GET_MEDIA_NAMES 0x0002 /* tx none, rx media_name(s) */
76 #define TIPC_CMD_GET_BEARER_NAMES 0x0003 /* tx none, rx bearer_name(s) */
77 #define TIPC_CMD_GET_LINKS 0x0004 /* tx net_addr, rx link_info(s) */
78 #define TIPC_CMD_SHOW_NAME_TABLE 0x0005 /* tx name_tbl_query, rx ultra_string */
79 #define TIPC_CMD_SHOW_PORTS 0x0006 /* tx none, rx ultra_string */
[all …]
/linux-3.3/net/mac80211/
Dwpa.c2 * Copyright 2002-2004, Instant802 Networks, Inc.
28 ieee80211_tx_h_michael_mic_add(struct ieee80211_tx_data *tx) in ieee80211_tx_h_michael_mic_add() argument
34 struct sk_buff *skb = tx->skb; in ieee80211_tx_h_michael_mic_add()
38 hdr = (struct ieee80211_hdr *)skb->data; in ieee80211_tx_h_michael_mic_add()
39 if (!tx->key || tx->key->conf.cipher != WLAN_CIPHER_SUITE_TKIP || in ieee80211_tx_h_michael_mic_add()
40 skb->len < 24 || !ieee80211_is_data_present(hdr->frame_control)) in ieee80211_tx_h_michael_mic_add()
43 hdrlen = ieee80211_hdrlen(hdr->frame_control); in ieee80211_tx_h_michael_mic_add()
44 if (skb->len < hdrlen) in ieee80211_tx_h_michael_mic_add()
47 data = skb->data + hdrlen; in ieee80211_tx_h_michael_mic_add()
48 data_len = skb->len - hdrlen; in ieee80211_tx_h_michael_mic_add()
[all …]
/linux-3.3/drivers/net/ethernet/broadcom/
Db44.h14 #define B44_BIST_STAT 0x000CUL /* Built-In Self-Test Status */
40 #define ISTAT_RX 0x00010000 /* RX Interrupt */
41 #define ISTAT_TX 0x01000000 /* TX Interrupt */
53 #define B44_TXBURST 0x00A0UL /* TX Max Burst Length */
54 #define B44_RXBURST 0x00A4UL /* RX Max Burst Length */
68 #define B44_DMATX_CTRL 0x0200UL /* DMA TX Control */
74 #define B44_DMATX_ADDR 0x0204UL /* DMA TX Descriptor Ring Address */
75 #define B44_DMATX_PTR 0x0208UL /* DMA TX Last Posted Descriptor */
76 #define B44_DMATX_STAT 0x020CUL /* DMA TX Current Active Desc. + Status */
91 #define B44_DMARX_CTRL 0x0210UL /* DMA RX Control */
[all …]
/linux-3.3/drivers/net/wan/
Dhd64570.h4 /* SCA HD64570 register definitions - all addresses for mode 0 (8086 MPU)
41 /* MSCI channel (port) 0 registers - offset 0x20
42 MSCI channel (port) 1 registers - offset 0x40 */
47 #define TRBL 0x00 /* TX/RX buffer L */
48 #define TRBH 0x01 /* TX/RX buffer H */
67 #define RXS 0x16 /* RX Clock Source */
68 #define TXS 0x17 /* TX Clock Source */
69 #define TRC0 0x18 /* TX Ready Control 0 */
70 #define TRC1 0x19 /* TX Ready Control 1 */
71 #define RRC 0x1A /* RX Ready Control */
[all …]

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