sound/arm/aaci.h

2  *  linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver
22 #define AACI_RXCR	0x000	/* 29 bits Control Rx FIFO */
23 #define AACI_TXCR	0x004	/* 17 bits Control Tx FIFO */
52  * TX/RX fifo control register (CR). P48
77 #define SR_RXTOFE	(1 << 11)	/* rx timeout fifo empty */
78 #define SR_TXTO		(1 << 10)	/* rx timeout fifo nonempty */
79 #define SR_TXU		(1 << 9)	/* tx underrun */
80 #define SR_RXO		(1 << 8)	/* rx overrun */
81 #define SR_TXB		(1 << 7)	/* tx busy */
82 #define SR_RXB		(1 << 6)	/* rx busy */
83 #define SR_TXFF		(1 << 5)	/* tx fifo full */
84 #define SR_RXFF		(1 << 4)	/* rx fifo full */
85 #define SR_TXHE		(1 << 3)	/* tx fifo half empty */
86 #define SR_RXHF		(1 << 2)	/* rx fifo half full */
87 #define SR_TXFE		(1 << 1)	/* tx fifo empty */
88 #define SR_RXFE		(1 << 0)	/* rx fifo empty */
93 #define ISR_RXTOFEINTR	(1 << 6)	/* rx fifo empty */
94 #define ISR_URINTR	(1 << 5)	/* tx underflow */
95 #define ISR_ORINTR	(1 << 4)	/* rx overflow */
96 #define ISR_RXINTR	(1 << 3)	/* rx fifo */
97 #define ISR_TXINTR	(1 << 2)	/* tx fifo intr */
98 #define ISR_RXTOINTR	(1 << 1)	/* tx timeout */
99 #define ISR_TXCINTR	(1 << 0)	/* tx complete */
115 #define ISR_RXTOFE	(1 << 6)	/* rx timeout fifo empty */
116 #define ISR_UR		(1 << 5)	/* tx fifo underrun */
117 #define ISR_OR		(1 << 4)	/* rx fifo overrun */
118 #define ISR_RX		(1 << 3)	/* rx interrupt status */
119 #define ISR_TX		(1 << 2)	/* tx interrupt status */
120 #define ISR_RXTO	(1 << 1)	/* rx timeout */
121 #define ISR_TXC		(1 << 0)	/* tx complete */
126 #define IE_RXTOFE	(1 << 6)	/* rx timeout fifo empty */
127 #define IE_UR		(1 << 5)	/* tx fifo underrun */
128 #define IE_OR		(1 << 4)	/* rx fifo overrun */
129 #define IE_RX		(1 << 3)	/* rx interrupt status */
130 #define IE_TX		(1 << 2)	/* tx interrupt status */
131 #define IE_RXTO		(1 << 1)	/* rx timeout */
132 #define IE_TXC		(1 << 0)	/* tx complete */
137 #define SLFR_RWIS	(1 << 13)	/* raw wake-up interrupt status */
139 #define SLFR_12TXE	(1 << 11)	/* slot 12 tx empty */
140 #define SLFR_12RXV	(1 << 10)	/* slot 12 rx valid */
141 #define SLFR_2TXE	(1 << 9)	/* slot 2 tx empty */
142 #define SLFR_2RXV	(1 << 8)	/* slot 2 rx valid */
143 #define SLFR_1TXE	(1 << 7)	/* slot 1 tx empty */
144 #define SLFR_1RXV	(1 << 6)	/* slot 1 rx valid */
145 #define SLFR_12TXB	(1 << 5)	/* slot 12 tx busy */
146 #define SLFR_12RXB	(1 << 4)	/* slot 12 rx busy */
147 #define SLFR_2TXB	(1 << 3)	/* slot 2 tx busy */
148 #define SLFR_2RXB	(1 << 2)	/* slot 2 rx busy */
149 #define SLFR_1TXB	(1 << 1)	/* slot 1 tx busy */
150 #define SLFR_1RXB	(1 << 0)	/* slot 1 rx busy */