Lines Matching +full:rx +full:- +full:tx

4   Copyright (C) 2007-2009  STMicroelectronics Ltd
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
34 if (unlikely(p->des01.tx.error_summary)) { in ndesc_get_tx_status()
35 if (unlikely(p->des01.tx.underflow_error)) { in ndesc_get_tx_status()
36 x->tx_underflow++; in ndesc_get_tx_status()
37 stats->tx_fifo_errors++; in ndesc_get_tx_status()
39 if (unlikely(p->des01.tx.no_carrier)) { in ndesc_get_tx_status()
40 x->tx_carrier++; in ndesc_get_tx_status()
41 stats->tx_carrier_errors++; in ndesc_get_tx_status()
43 if (unlikely(p->des01.tx.loss_carrier)) { in ndesc_get_tx_status()
44 x->tx_losscarrier++; in ndesc_get_tx_status()
45 stats->tx_carrier_errors++; in ndesc_get_tx_status()
47 if (unlikely((p->des01.tx.excessive_deferral) || in ndesc_get_tx_status()
48 (p->des01.tx.excessive_collisions) || in ndesc_get_tx_status()
49 (p->des01.tx.late_collision))) in ndesc_get_tx_status()
50 stats->collisions += p->des01.tx.collision_count; in ndesc_get_tx_status()
51 ret = -1; in ndesc_get_tx_status()
54 if (p->des01.etx.vlan_frame) { in ndesc_get_tx_status()
55 CHIP_DBG(KERN_INFO "GMAC TX status: VLAN frame\n"); in ndesc_get_tx_status()
56 x->tx_vlan++; in ndesc_get_tx_status()
59 if (unlikely(p->des01.tx.deferred)) in ndesc_get_tx_status()
60 x->tx_deferred++; in ndesc_get_tx_status()
67 return p->des01.tx.buffer1_size; in ndesc_get_tx_len()
80 if (unlikely(p->des01.rx.last_descriptor == 0)) { in ndesc_get_rx_status()
83 stats->rx_length_errors++; in ndesc_get_rx_status()
87 if (unlikely(p->des01.rx.error_summary)) { in ndesc_get_rx_status()
88 if (unlikely(p->des01.rx.descriptor_error)) in ndesc_get_rx_status()
89 x->rx_desc++; in ndesc_get_rx_status()
90 if (unlikely(p->des01.rx.sa_filter_fail)) in ndesc_get_rx_status()
91 x->sa_filter_fail++; in ndesc_get_rx_status()
92 if (unlikely(p->des01.rx.overflow_error)) in ndesc_get_rx_status()
93 x->overflow_error++; in ndesc_get_rx_status()
94 if (unlikely(p->des01.rx.ipc_csum_error)) in ndesc_get_rx_status()
95 x->ipc_csum_error++; in ndesc_get_rx_status()
96 if (unlikely(p->des01.rx.collision)) { in ndesc_get_rx_status()
97 x->rx_collision++; in ndesc_get_rx_status()
98 stats->collisions++; in ndesc_get_rx_status()
100 if (unlikely(p->des01.rx.crc_error)) { in ndesc_get_rx_status()
101 x->rx_crc++; in ndesc_get_rx_status()
102 stats->rx_crc_errors++; in ndesc_get_rx_status()
106 if (unlikely(p->des01.rx.dribbling)) in ndesc_get_rx_status()
107 x->dribbling_bit++; in ndesc_get_rx_status()
109 if (unlikely(p->des01.rx.length_error)) { in ndesc_get_rx_status()
110 x->rx_length++; in ndesc_get_rx_status()
113 if (unlikely(p->des01.rx.mii_error)) { in ndesc_get_rx_status()
114 x->rx_mii++; in ndesc_get_rx_status()
118 if (p->des01.rx.vlan_tag) in ndesc_get_rx_status()
119 x->vlan_tag++; in ndesc_get_rx_status()
129 p->des01.rx.own = 1; in ndesc_init_rx_desc()
130 p->des01.rx.buffer1_size = BUF_SIZE_2KiB - 1; in ndesc_init_rx_desc()
132 ndesc_rx_set_on_ring_chain(p, (i == ring_size - 1)); in ndesc_init_rx_desc()
135 p->des01.rx.disable_ic = 1; in ndesc_init_rx_desc()
144 p->des01.tx.own = 0; in ndesc_init_tx_desc()
145 ndesc_tx_set_on_ring_chain(p, (i == (ring_size - 1))); in ndesc_init_tx_desc()
152 return p->des01.tx.own; in ndesc_get_tx_owner()
157 return p->des01.rx.own; in ndesc_get_rx_owner()
162 p->des01.tx.own = 1; in ndesc_set_tx_owner()
167 p->des01.rx.own = 1; in ndesc_set_rx_owner()
172 return p->des01.tx.last_segment; in ndesc_get_tx_ls()
177 int ter = p->des01.tx.end_ring; in ndesc_release_tx_desc()
186 p->des01.tx.first_segment = is_fs; in ndesc_prepare_tx_desc()
190 p->des01.tx.checksum_insertion = cic_full; in ndesc_prepare_tx_desc()
195 p->des01.tx.interrupt = 0; in ndesc_clear_tx_ic()
200 p->des01.tx.last_segment = 1; in ndesc_close_tx_desc()
201 p->des01.tx.interrupt = 1; in ndesc_close_tx_desc()
206 return p->des01.rx.frame_length; in ndesc_get_rx_frame_len()