net/wan/hd64570.h

4 /* SCA HD64570 register definitions - all addresses for mode 0 (8086 MPU)
41 /* MSCI channel (port) 0 registers - offset 0x20
42    MSCI channel (port) 1 registers - offset 0x40 */
47 #define TRBL   0x00		/* TX/RX buffer L */
48 #define TRBH   0x01		/* TX/RX buffer H */
67 #define RXS    0x16		/* RX Clock Source */
68 #define TXS    0x17		/* TX Clock Source */
69 #define TRC0   0x18		/* TX Ready Control 0 */
70 #define TRC1   0x19		/* TX Ready Control 1 */
71 #define RRC    0x1A		/* RX Ready Control */
76 /* Timer channel 0 (port 0 RX) registers - offset 0x60
77    Timer channel 1 (port 0 TX) registers - offset 0x68
78    Timer channel 2 (port 1 RX) registers - offset 0x70
79    Timer channel 3 (port 1 TX) registers - offset 0x78
87 #define TCNTL  0x00		/* Up-counter L */
88 #define TCNTH  0x01		/* Up-counter H */
96 /* DMA channel 0 (port 0 RX) registers - offset 0x80
97    DMA channel 1 (port 0 TX) registers - offset 0xA0
98    DMA channel 2 (port 1 RX) registers - offset 0xC0
99    DMA channel 3 (port 1 TX) registers - offset 0xE0
111 #define DARL   0x00		/* RX Destination Addr L (single block) */
112 #define DARH   0x01		/* RX Destination Addr H (single block) */
113 #define DARB   0x02		/* RX Destination Addr B (single block) */
115 #define SARL   0x04		/* TX Source Address L (single block) */
116 #define SARH   0x05		/* TX Source Address H (single block) */
117 #define SARB   0x06		/* TX Source Address B (single block) */
125 #define BFLL   0x0C		/* RX Receive Buffer Length L (chained block)*/
126 #define BFLH   0x0D		/* RX Receive Buffer Length H (chained block)*/
155 	u8 unused;		/* pads to 2-byte boundary */
174 #define DIR_EOME      0x40      /* Frame Transfer Completed (chained-block) */
175 #define DIR_BOFE      0x20      /* Buffer Overflow/Underflow (chained-block)*/
176 #define DIR_COFE      0x10      /* Counter Overflow (chained-block) */
180 #define DSR_EOM       0x40      /* Frame Transfer Completed (chained-block) */
181 #define DSR_BOF       0x20      /* Buffer Overflow/Underflow (chained-block)*/
182 #define DSR_COF       0x10      /* Counter Overflow (chained-block) */
194 #define MD0_HDLC      0x80	/* Bit-sync HDLC mode */
196 #define MD0_CRC_CCITT 0x02	/* CCITT CRC instead of CRC-16 */
197 #define MD0_CRC_PR1   0x01	/* Initial all-ones instead of all-zeros */
216 #define ST0_TXRDY     0x02	/* TX ready */
217 #define ST0_RXRDY     0x01	/* RX ready */
219 #define ST1_UDRN      0x80	/* MSCI TX underrun */
222 #define ST3_CTS       0x08	/* modem input - /CTS */
223 #define ST3_DCD       0x04	/* modem input - /DCD */
225 #define IE0_TXINT     0x80	/* TX INT MSCI interrupt enable */
226 #define IE0_RXINTA    0x40	/* RX INT A MSCI interrupt enable */
227 #define IE1_UDRN      0x80	/* TX underrun MSCI interrupt enable */
233 /* TX and RX Clock Source - RXS and TXS */
235 #define CLK_LINE_RX   0x00	/* TX/RX clock line input */
236 #define CLK_LINE_TX   0x00	/* TX/RX line input */
239 #define CLK_RXCLK_TX  0x60	/* TX clock from RX clock */