Lines Matching +full:rx +full:- +full:tx
4 * Copyright (c) 2007-2011, Code Aurora Forum. All rights reserved.
20 * RX wakeup.
21 * UART wakeup can be triggered by RX activity (using a wakeup GPIO on the
22 * UART RX pin). This should only be used if there is not a wakeup
23 * GPIO on the UART CTS, and the first RX byte is known (for example, with the
24 * Bluetooth Texas Instruments HCILL protocol), since the first RX byte will
46 #include <linux/dma-mapping.h>
205 /* Rx DMA request states */
219 MSM_HS_CLK_REQUEST_OFF, /* disable after TX and RX flushed */
234 * @tx_ready_int_en: ok to dma more tx?
235 * @dma_in_flight: tx dma in progress
244 * This structure describes a single Tx DMA transaction. MSM DMA
247 * single DMA 'command'. In our case each Tx transaction consists
264 * @flush: Rx DMA request state
271 * @buffer: destination buffer for RX DMA
273 * @pool: dma pool out of which coherent rx buffer is allocated
274 * @tty_work: private work-queue for tty flip buffer push task
276 * This structure describes a single Rx DMA transaction. Rx DMA
295 * @irq: IRQ line to be configured as interrupt source on Rx activity
297 * @rx_to_inject: extra character to be inserted to Rx tty on wakeup
300 * This is an optional structure required for UART Rx GPIO IRQ based
301 * wakeup from low power state. UART wakeup can be triggered by RX activity
302 * (using a wakeup GPIO on the UART RX pin). This should only be used if
303 * there is not a wakeup GPIO on the UART CTS, and the first RX byte is
305 * since the first RX byte will always be lost. RTS will be asserted even
320 * @tx: Tx transaction related data structure
321 * @rx: Rx transaction related data structure
322 * @dma_tx_channel: Tx DMA command channel
323 * @dma_rx_channel Rx DMA command channel
324 * @dma_tx_crci: Tx channel rate control interface number
325 * @dma_rx_crci: Rx channel rate control interface number
339 struct msm_hs_tx tx; member
340 struct msm_hs_rx rx; member
374 return (msm_uport->rx_wakeup.irq >= 0); in use_low_power_rx_wakeup()
380 return ioread32(uport->membase + offset); in msm_hs_read()
386 iowrite32(value, uport->membase + offset); in msm_hs_write()
391 iounmap(port->membase); in msm_hs_release_port()
396 port->membase = ioremap(port->mapbase, PAGE_SIZE); in msm_hs_request_port()
397 if (unlikely(!port->membase)) in msm_hs_request_port()
398 return -ENOMEM; in msm_hs_request_port()
411 if (pdev->id < 0 || pdev->id >= UARTDM_NR) { in msm_hs_remove()
412 printk(KERN_ERR "Invalid plaform device ID = %d\n", pdev->id); in msm_hs_remove()
413 return -EINVAL; in msm_hs_remove()
416 msm_uport = &q_uart_port[pdev->id]; in msm_hs_remove()
417 dev = msm_uport->uport.dev; in msm_hs_remove()
419 dma_unmap_single(dev, msm_uport->rx.mapped_cmd_ptr, sizeof(dmov_box), in msm_hs_remove()
421 dma_pool_free(msm_uport->rx.pool, msm_uport->rx.buffer, in msm_hs_remove()
422 msm_uport->rx.rbuffer); in msm_hs_remove()
423 dma_pool_destroy(msm_uport->rx.pool); in msm_hs_remove()
425 dma_unmap_single(dev, msm_uport->rx.cmdptr_dmaaddr, sizeof(u32), in msm_hs_remove()
427 dma_unmap_single(dev, msm_uport->tx.mapped_cmd_ptr_ptr, sizeof(u32), in msm_hs_remove()
429 dma_unmap_single(dev, msm_uport->tx.mapped_cmd_ptr, sizeof(dmov_box), in msm_hs_remove()
432 uart_remove_one_port(&msm_hs_driver, &msm_uport->uport); in msm_hs_remove()
433 clk_put(msm_uport->clk); in msm_hs_remove()
435 /* Free the tx resources */ in msm_hs_remove()
436 kfree(msm_uport->tx.command_ptr); in msm_hs_remove()
437 kfree(msm_uport->tx.command_ptr_ptr); in msm_hs_remove()
439 /* Free the rx resources */ in msm_hs_remove()
440 kfree(msm_uport->rx.command_ptr); in msm_hs_remove()
441 kfree(msm_uport->rx.command_ptr_ptr); in msm_hs_remove()
443 iounmap(msm_uport->uport.membase); in msm_hs_remove()
453 ret = clk_enable(msm_uport->clk); in msm_hs_init_clk_locked()
460 ret = clk_set_rate(msm_uport->clk, uport->uartclk); in msm_hs_init_clk_locked()
463 clk_disable(msm_uport->clk); in msm_hs_init_clk_locked()
467 msm_uport->clk_state = MSM_HS_CLK_ON; in msm_hs_init_clk_locked()
478 msm_uport->exit_lpm_cb) in msm_hs_pm()
484 clk_enable(msm_uport->clk); in msm_hs_pm()
487 clk_disable(msm_uport->clk); in msm_hs_pm()
490 dev_err(uport->dev, "msm_serial: Unknown PM state %d\n", in msm_hs_pm()
593 uport->uartclk = bps * 16; in msm_hs_set_bps_locked()
595 uport->uartclk = UARTCLK; in msm_hs_set_bps_locked()
597 if (clk_set_rate(msm_uport->clk, uport->uartclk)) { in msm_hs_set_bps_locked()
621 unsigned int c_cflag = termios->c_cflag; in msm_hs_set_termios()
624 spin_lock_irqsave(&uport->lock, flags); in msm_hs_set_termios()
625 clk_enable(msm_uport->clk); in msm_hs_set_termios()
688 uport->ignore_status_mask = termios->c_iflag & INPCK; in msm_hs_set_termios()
689 uport->ignore_status_mask |= termios->c_iflag & IGNPAR; in msm_hs_set_termios()
690 uport->read_status_mask = (termios->c_cflag & CREAD); in msm_hs_set_termios()
700 if (msm_uport->rx.flush == FLUSH_NONE) { in msm_hs_set_termios()
701 msm_uport->rx.flush = FLUSH_IGNORE; in msm_hs_set_termios()
702 msm_dmov_stop_cmd(msm_uport->dma_rx_channel, NULL, 1); in msm_hs_set_termios()
705 msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg); in msm_hs_set_termios()
707 clk_disable(msm_uport->clk); in msm_hs_set_termios()
708 spin_unlock_irqrestore(&uport->lock, flags); in msm_hs_set_termios()
721 clk_enable(msm_uport->clk); in msm_hs_tx_empty()
727 clk_disable(msm_uport->clk); in msm_hs_tx_empty()
741 msm_uport->tx.tx_ready_int_en = 0; in msm_hs_stop_tx_locked()
757 clk_enable(msm_uport->clk); in msm_hs_stop_rx_locked()
765 if (msm_uport->rx.flush == FLUSH_NONE) in msm_hs_stop_rx_locked()
766 msm_dmov_stop_cmd(msm_uport->dma_rx_channel, NULL, 1); in msm_hs_stop_rx_locked()
768 if (msm_uport->rx.flush != FLUSH_SHUTDOWN) in msm_hs_stop_rx_locked()
769 msm_uport->rx.flush = FLUSH_STOP; in msm_hs_stop_rx_locked()
771 clk_disable(msm_uport->clk); in msm_hs_stop_rx_locked()
781 struct msm_hs_tx *tx = &msm_uport->tx; in msm_hs_submit_tx_locked() local
782 struct circ_buf *tx_buf = &msm_uport->uport.state->xmit; in msm_hs_submit_tx_locked()
784 if (uart_circ_empty(tx_buf) || uport->state->port.tty->stopped) { in msm_hs_submit_tx_locked()
789 tx->dma_in_flight = 1; in msm_hs_submit_tx_locked()
796 left = UART_XMIT_SIZE - tx_buf->tail; in msm_hs_submit_tx_locked()
801 src_addr = tx->dma_base + tx_buf->tail; in msm_hs_submit_tx_locked()
802 dma_sync_single_for_device(uport->dev, src_addr, tx_count, in msm_hs_submit_tx_locked()
805 tx->command_ptr->num_rows = (((tx_count + 15) >> 4) << 16) | in msm_hs_submit_tx_locked()
807 tx->command_ptr->src_row_addr = src_addr; in msm_hs_submit_tx_locked()
809 dma_sync_single_for_device(uport->dev, tx->mapped_cmd_ptr, in msm_hs_submit_tx_locked()
812 *tx->command_ptr_ptr = CMD_PTR_LP | DMOV_CMD_ADDR(tx->mapped_cmd_ptr); in msm_hs_submit_tx_locked()
814 dma_sync_single_for_device(uport->dev, tx->mapped_cmd_ptr_ptr, in msm_hs_submit_tx_locked()
818 tx->tx_count = tx_count; in msm_hs_submit_tx_locked()
822 msm_uport->imr_reg &= ~UARTDM_ISR_TX_READY_BMSK; in msm_hs_submit_tx_locked()
823 msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg); in msm_hs_submit_tx_locked()
824 msm_dmov_enqueue_cmd(msm_uport->dma_tx_channel, &tx->xfer); in msm_hs_submit_tx_locked()
835 msm_uport->imr_reg |= UARTDM_ISR_RXLEV_BMSK; in msm_hs_start_rx_locked()
836 msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg); in msm_hs_start_rx_locked()
838 msm_uport->rx.flush = FLUSH_NONE; in msm_hs_start_rx_locked()
839 msm_dmov_enqueue_cmd(msm_uport->dma_rx_channel, &msm_uport->rx.xfer); in msm_hs_start_rx_locked()
841 /* might have finished RX and be ready to clock off */ in msm_hs_start_rx_locked()
842 hrtimer_start(&msm_uport->clk_off_timer, msm_uport->clk_off_delay, in msm_hs_start_rx_locked()
851 clk_enable(msm_uport->clk); in msm_hs_start_tx_locked()
853 if (msm_uport->exit_lpm_cb) in msm_hs_start_tx_locked()
854 msm_uport->exit_lpm_cb(uport); in msm_hs_start_tx_locked()
856 if (msm_uport->tx.tx_ready_int_en == 0) { in msm_hs_start_tx_locked()
857 msm_uport->tx.tx_ready_int_en = 1; in msm_hs_start_tx_locked()
861 clk_disable(msm_uport->clk); in msm_hs_start_tx_locked()
882 msm_uport = container_of(cmd_ptr, struct msm_hs_port, tx.xfer); in msm_hs_dmov_tx_callback()
884 spin_lock_irqsave(&msm_uport->uport.lock, flags); in msm_hs_dmov_tx_callback()
885 clk_enable(msm_uport->clk); in msm_hs_dmov_tx_callback()
887 msm_uport->imr_reg |= UARTDM_ISR_TX_READY_BMSK; in msm_hs_dmov_tx_callback()
888 msm_hs_write(&msm_uport->uport, UARTDM_IMR_ADDR, msm_uport->imr_reg); in msm_hs_dmov_tx_callback()
890 clk_disable(msm_uport->clk); in msm_hs_dmov_tx_callback()
891 spin_unlock_irqrestore(&msm_uport->uport.lock, flags); in msm_hs_dmov_tx_callback()
915 msm_uport = container_of(cmd_ptr, struct msm_hs_port, rx.xfer); in msm_hs_dmov_rx_callback()
916 uport = &msm_uport->uport; in msm_hs_dmov_rx_callback()
918 spin_lock_irqsave(&uport->lock, flags); in msm_hs_dmov_rx_callback()
919 clk_enable(msm_uport->clk); in msm_hs_dmov_rx_callback()
921 tty = uport->state->port.tty; in msm_hs_dmov_rx_callback()
929 (uport->read_status_mask & CREAD))) { in msm_hs_dmov_rx_callback()
931 uport->icount.buf_overrun++; in msm_hs_dmov_rx_callback()
935 if (!(uport->ignore_status_mask & INPCK)) in msm_hs_dmov_rx_callback()
940 uport->icount.parity++; in msm_hs_dmov_rx_callback()
942 if (uport->ignore_status_mask & IGNPAR) in msm_hs_dmov_rx_callback()
949 if (msm_uport->clk_req_off_state == CLK_REQ_OFF_FLUSH_ISSUED) in msm_hs_dmov_rx_callback()
950 msm_uport->clk_req_off_state = CLK_REQ_OFF_RXSTALE_FLUSHED; in msm_hs_dmov_rx_callback()
952 flush = msm_uport->rx.flush; in msm_hs_dmov_rx_callback()
956 msm_uport->rx.flush = FLUSH_SHUTDOWN; in msm_hs_dmov_rx_callback()
962 if (0 != (uport->read_status_mask & CREAD)) { in msm_hs_dmov_rx_callback()
963 retval = tty_insert_flip_string(tty, msm_uport->rx.buffer, in msm_hs_dmov_rx_callback()
971 clk_disable(msm_uport->clk); in msm_hs_dmov_rx_callback()
973 spin_unlock_irqrestore(&uport->lock, flags); in msm_hs_dmov_rx_callback()
976 queue_work(msm_hs_workqueue, &msm_uport->rx.tty_work); in msm_hs_dmov_rx_callback()
982 container_of(work, struct msm_hs_port, rx.tty_work); in msm_hs_tty_flip_buffer_work()
983 struct tty_struct *tty = msm_uport->uport.state->port.tty; in msm_hs_tty_flip_buffer_work()
992 * indicate clear to send and count on the TX FIFO to block when
995 * - TIOCM_DCD
996 * - TIOCM_CTS
997 * - TIOCM_DSR
998 * - TIOCM_RI
1007 * True enables UART auto RFR, which indicates we are ready for data if the RX
1018 /* enable auto ready-for-receiving */ in set_rfr_locked()
1022 /* disable auto ready-for-receiving */ in set_rfr_locked()
1039 clk_enable(msm_uport->clk); in msm_hs_set_mctrl_locked()
1044 clk_disable(msm_uport->clk); in msm_hs_set_mctrl_locked()
1052 clk_enable(msm_uport->clk); in msm_hs_enable_ms_locked()
1055 msm_uport->imr_reg |= UARTDM_ISR_DELTA_CTS_BMSK; in msm_hs_enable_ms_locked()
1056 msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg); in msm_hs_enable_ms_locked()
1058 clk_disable(msm_uport->clk); in msm_hs_enable_ms_locked()
1072 clk_enable(msm_uport->clk); in msm_hs_break_ctl()
1074 clk_disable(msm_uport->clk); in msm_hs_break_ctl()
1081 spin_lock_irqsave(&uport->lock, flags); in msm_hs_config_port()
1083 uport->type = PORT_MSM; in msm_hs_config_port()
1086 spin_unlock_irqrestore(&uport->lock, flags); in msm_hs_config_port()
1094 clk_enable(msm_uport->clk); in msm_hs_handle_delta_cts_locked()
1098 uport->icount.cts++; in msm_hs_handle_delta_cts_locked()
1100 clk_disable(msm_uport->clk); in msm_hs_handle_delta_cts_locked()
1103 wake_up_interruptible(&uport->state->port.delta_msr_wait); in msm_hs_handle_delta_cts_locked()
1106 /* check if the TX path is flushed, and if so clock off
1108 * -1 did not clock off, do not retry
1115 struct circ_buf *tx_buf = &uport->state->xmit; in msm_hs_check_clock_off_locked()
1117 /* Cancel if tx tty buffer is not empty, dma is in flight, in msm_hs_check_clock_off_locked()
1118 * or tx fifo is not empty, or rx fifo is not empty */ in msm_hs_check_clock_off_locked()
1119 if (msm_uport->clk_state != MSM_HS_CLK_REQUEST_OFF || in msm_hs_check_clock_off_locked()
1120 !uart_circ_empty(tx_buf) || msm_uport->tx.dma_in_flight || in msm_hs_check_clock_off_locked()
1121 (msm_uport->imr_reg & UARTDM_ISR_TXLEV_BMSK) || in msm_hs_check_clock_off_locked()
1122 !(msm_uport->imr_reg & UARTDM_ISR_RXLEV_BMSK)) { in msm_hs_check_clock_off_locked()
1123 return -1; in msm_hs_check_clock_off_locked()
1132 switch (msm_uport->clk_req_off_state) { in msm_hs_check_clock_off_locked()
1134 msm_uport->clk_req_off_state = CLK_REQ_OFF_RXSTALE_ISSUED; in msm_hs_check_clock_off_locked()
1136 return 0; /* RXSTALE flush not complete - retry */ in msm_hs_check_clock_off_locked()
1139 return 0; /* RXSTALE flush not complete - retry */ in msm_hs_check_clock_off_locked()
1144 if (msm_uport->rx.flush != FLUSH_SHUTDOWN) { in msm_hs_check_clock_off_locked()
1145 if (msm_uport->rx.flush == FLUSH_NONE) in msm_hs_check_clock_off_locked()
1151 clk_disable(msm_uport->clk); in msm_hs_check_clock_off_locked()
1152 msm_uport->clk_state = MSM_HS_CLK_OFF; in msm_hs_check_clock_off_locked()
1155 msm_uport->rx_wakeup.ignore = 1; in msm_hs_check_clock_off_locked()
1156 enable_irq(msm_uport->rx_wakeup.irq); in msm_hs_check_clock_off_locked()
1167 struct uart_port *uport = &msm_uport->uport; in msm_hs_clk_off_retry()
1169 spin_lock_irqsave(&uport->lock, flags); in msm_hs_clk_off_retry()
1172 hrtimer_forward_now(timer, msm_uport->clk_off_delay); in msm_hs_clk_off_retry()
1176 spin_unlock_irqrestore(&uport->lock, flags); in msm_hs_clk_off_retry()
1186 struct uart_port *uport = &msm_uport->uport; in msm_hs_isr()
1187 struct circ_buf *tx_buf = &uport->state->xmit; in msm_hs_isr()
1188 struct msm_hs_tx *tx = &msm_uport->tx; in msm_hs_isr() local
1189 struct msm_hs_rx *rx = &msm_uport->rx; in msm_hs_isr() local
1191 spin_lock_irqsave(&uport->lock, flags); in msm_hs_isr()
1195 /* Uart RX starting */ in msm_hs_isr()
1197 msm_uport->imr_reg &= ~UARTDM_ISR_RXLEV_BMSK; in msm_hs_isr()
1198 msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg); in msm_hs_isr()
1200 /* Stale rx interrupt */ in msm_hs_isr()
1205 if (msm_uport->clk_req_off_state == CLK_REQ_OFF_RXSTALE_ISSUED) in msm_hs_isr()
1206 msm_uport->clk_req_off_state = in msm_hs_isr()
1208 if (rx->flush == FLUSH_NONE) { in msm_hs_isr()
1209 rx->flush = FLUSH_DATA_READY; in msm_hs_isr()
1210 msm_dmov_stop_cmd(msm_uport->dma_rx_channel, NULL, 1); in msm_hs_isr()
1213 /* tx ready interrupt */ in msm_hs_isr()
1215 /* Clear TX Ready */ in msm_hs_isr()
1218 if (msm_uport->clk_state == MSM_HS_CLK_REQUEST_OFF) { in msm_hs_isr()
1219 msm_uport->imr_reg |= UARTDM_ISR_TXLEV_BMSK; in msm_hs_isr()
1221 msm_uport->imr_reg); in msm_hs_isr()
1224 /* Complete DMA TX transactions and submit new transactions */ in msm_hs_isr()
1225 tx_buf->tail = (tx_buf->tail + tx->tx_count) & ~UART_XMIT_SIZE; in msm_hs_isr()
1227 tx->dma_in_flight = 0; in msm_hs_isr()
1229 uport->icount.tx += tx->tx_count; in msm_hs_isr()
1230 if (tx->tx_ready_int_en) in msm_hs_isr()
1237 /* TX FIFO is empty */ in msm_hs_isr()
1238 msm_uport->imr_reg &= ~UARTDM_ISR_TXLEV_BMSK; in msm_hs_isr()
1239 msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg); in msm_hs_isr()
1241 hrtimer_start(&msm_uport->clk_off_timer, in msm_hs_isr()
1242 msm_uport->clk_off_delay, in msm_hs_isr()
1250 spin_unlock_irqrestore(&uport->lock, flags); in msm_hs_isr()
1259 if (msm_uport->clk_state == MSM_HS_CLK_ON) { in msm_hs_request_clock_off_locked()
1260 msm_uport->clk_state = MSM_HS_CLK_REQUEST_OFF; in msm_hs_request_clock_off_locked()
1261 msm_uport->clk_req_off_state = CLK_REQ_OFF_START; in msm_hs_request_clock_off_locked()
1264 msm_uport->imr_reg |= UARTDM_ISR_TXLEV_BMSK; in msm_hs_request_clock_off_locked()
1265 msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg); in msm_hs_request_clock_off_locked()
1270 * msm_hs_request_clock_off - request to (i.e. asynchronously) turn off uart
1271 * clock once pending TX is flushed and Rx DMA command is terminated.
1275 * waits to complete all pending tx transactions, flushes ongoing Rx DMA
1276 * command and terminates UART side Rx transaction, puts UART HW in non DMA
1285 spin_lock_irqsave(&uport->lock, flags); in msm_hs_request_clock_off()
1287 spin_unlock_irqrestore(&uport->lock, flags); in msm_hs_request_clock_off()
1295 switch (msm_uport->clk_state) { in msm_hs_request_clock_on_locked()
1297 clk_enable(msm_uport->clk); in msm_hs_request_clock_on_locked()
1298 disable_irq_nosync(msm_uport->rx_wakeup.irq); in msm_hs_request_clock_on_locked()
1299 /* fall-through */ in msm_hs_request_clock_on_locked()
1301 if (msm_uport->rx.flush == FLUSH_STOP || in msm_hs_request_clock_on_locked()
1302 msm_uport->rx.flush == FLUSH_SHUTDOWN) { in msm_hs_request_clock_on_locked()
1308 hrtimer_try_to_cancel(&msm_uport->clk_off_timer); in msm_hs_request_clock_on_locked()
1309 if (msm_uport->rx.flush == FLUSH_SHUTDOWN) in msm_hs_request_clock_on_locked()
1313 if (msm_uport->rx.flush == FLUSH_STOP) in msm_hs_request_clock_on_locked()
1314 msm_uport->rx.flush = FLUSH_IGNORE; in msm_hs_request_clock_on_locked()
1315 msm_uport->clk_state = MSM_HS_CLK_ON; in msm_hs_request_clock_on_locked()
1325 * msm_hs_request_clock_on - Switch the device from partially active low
1330 * and enqueues an Rx DMA command if the device was in partially active
1337 spin_lock_irqsave(&uport->lock, flags); in msm_hs_request_clock_on()
1339 spin_unlock_irqrestore(&uport->lock, flags); in msm_hs_request_clock_on()
1347 struct uart_port *uport = &msm_uport->uport; in msm_hs_rx_wakeup_isr()
1350 spin_lock_irqsave(&uport->lock, flags); in msm_hs_rx_wakeup_isr()
1351 if (msm_uport->clk_state == MSM_HS_CLK_OFF) { in msm_hs_rx_wakeup_isr()
1352 /* ignore the first irq - it is a pending irq that occurred in msm_hs_rx_wakeup_isr()
1354 if (msm_uport->rx_wakeup.ignore) in msm_hs_rx_wakeup_isr()
1355 msm_uport->rx_wakeup.ignore = 0; in msm_hs_rx_wakeup_isr()
1361 /* the uart was clocked off during an rx, wake up and in msm_hs_rx_wakeup_isr()
1362 * optionally inject char into tty rx */ in msm_hs_rx_wakeup_isr()
1364 if (msm_uport->rx_wakeup.inject_rx) { in msm_hs_rx_wakeup_isr()
1365 tty = uport->state->port.tty; in msm_hs_rx_wakeup_isr()
1367 msm_uport->rx_wakeup.rx_to_inject, in msm_hs_rx_wakeup_isr()
1369 queue_work(msm_hs_workqueue, &msm_uport->rx.tty_work); in msm_hs_rx_wakeup_isr()
1373 spin_unlock_irqrestore(&uport->lock, flags); in msm_hs_rx_wakeup_isr()
1380 return (port->type == PORT_MSM) ? "MSM_HS_UART" : NULL; in msm_hs_type()
1391 struct circ_buf *tx_buf = &uport->state->xmit; in msm_hs_startup()
1392 struct msm_hs_tx *tx = &msm_uport->tx; in msm_hs_startup() local
1393 struct msm_hs_rx *rx = &msm_uport->rx; in msm_hs_startup() local
1395 rfr_level = uport->fifosize; in msm_hs_startup()
1397 rfr_level -= 16; in msm_hs_startup()
1399 tx->dma_base = dma_map_single(uport->dev, tx_buf->buf, UART_XMIT_SIZE, in msm_hs_startup()
1402 /* do not let tty layer execute RX in global workqueue, use a in msm_hs_startup()
1404 uport->state->port.tty->low_latency = 1; in msm_hs_startup()
1421 /* Make sure RXSTALE count is non-zero */ in msm_hs_startup()
1432 /* Reset TX */ in msm_hs_startup()
1446 /* Initialize the tx */ in msm_hs_startup()
1447 tx->tx_ready_int_en = 0; in msm_hs_startup()
1448 tx->dma_in_flight = 0; in msm_hs_startup()
1450 tx->xfer.complete_func = msm_hs_dmov_tx_callback; in msm_hs_startup()
1451 tx->xfer.execute_func = NULL; in msm_hs_startup()
1453 tx->command_ptr->cmd = CMD_LC | in msm_hs_startup()
1454 CMD_DST_CRCI(msm_uport->dma_tx_crci) | CMD_MODE_BOX; in msm_hs_startup()
1456 tx->command_ptr->src_dst_len = (MSM_UARTDM_BURST_SIZE << 16) in msm_hs_startup()
1459 tx->command_ptr->row_offset = (MSM_UARTDM_BURST_SIZE << 16); in msm_hs_startup()
1461 tx->command_ptr->dst_row_addr = in msm_hs_startup()
1462 msm_uport->uport.mapbase + UARTDM_TF_ADDR; in msm_hs_startup()
1466 rx->xfer.complete_func = msm_hs_dmov_rx_callback; in msm_hs_startup()
1467 rx->xfer.execute_func = NULL; in msm_hs_startup()
1469 rx->command_ptr->cmd = CMD_LC | in msm_hs_startup()
1470 CMD_SRC_CRCI(msm_uport->dma_rx_crci) | CMD_MODE_BOX; in msm_hs_startup()
1472 rx->command_ptr->src_dst_len = (MSM_UARTDM_BURST_SIZE << 16) in msm_hs_startup()
1474 rx->command_ptr->row_offset = MSM_UARTDM_BURST_SIZE; in msm_hs_startup()
1475 rx->command_ptr->src_row_addr = uport->mapbase + UARTDM_RF_ADDR; in msm_hs_startup()
1478 msm_uport->imr_reg |= UARTDM_ISR_RXSTALE_BMSK; in msm_hs_startup()
1480 msm_uport->imr_reg |= UARTDM_ISR_CURRENT_CTS_BMSK; in msm_hs_startup()
1482 msm_hs_write(uport, UARTDM_TFWR_ADDR, 0); /* TXLEV on empty TX fifo */ in msm_hs_startup()
1485 ret = request_irq(uport->irq, msm_hs_isr, IRQF_TRIGGER_HIGH, in msm_hs_startup()
1492 ret = request_irq(msm_uport->rx_wakeup.irq, in msm_hs_startup()
1498 free_irq(uport->irq, msm_uport); in msm_hs_startup()
1501 disable_irq(msm_uport->rx_wakeup.irq); in msm_hs_startup()
1504 spin_lock_irqsave(&uport->lock, flags); in msm_hs_startup()
1509 spin_unlock_irqrestore(&uport->lock, flags); in msm_hs_startup()
1510 ret = pm_runtime_set_active(uport->dev); in msm_hs_startup()
1512 dev_err(uport->dev, "set active error:%d\n", ret); in msm_hs_startup()
1513 pm_runtime_enable(uport->dev); in msm_hs_startup()
1519 dma_unmap_single(uport->dev, tx->dma_base, in msm_hs_startup()
1524 /* Initialize tx and rx data structures */
1529 struct msm_hs_tx *tx = &msm_uport->tx; in uartdm_init_port() local
1530 struct msm_hs_rx *rx = &msm_uport->rx; in uartdm_init_port() local
1533 tx->command_ptr = kmalloc(sizeof(dmov_box), GFP_KERNEL | __GFP_DMA); in uartdm_init_port()
1534 if (!tx->command_ptr) in uartdm_init_port()
1535 return -ENOMEM; in uartdm_init_port()
1537 tx->command_ptr_ptr = kmalloc(sizeof(u32), GFP_KERNEL | __GFP_DMA); in uartdm_init_port()
1538 if (!tx->command_ptr_ptr) { in uartdm_init_port()
1539 ret = -ENOMEM; in uartdm_init_port()
1543 tx->mapped_cmd_ptr = dma_map_single(uport->dev, tx->command_ptr, in uartdm_init_port()
1545 tx->mapped_cmd_ptr_ptr = dma_map_single(uport->dev, in uartdm_init_port()
1546 tx->command_ptr_ptr, in uartdm_init_port()
1548 tx->xfer.cmdptr = DMOV_CMD_ADDR(tx->mapped_cmd_ptr_ptr); in uartdm_init_port()
1550 init_waitqueue_head(&rx->wait); in uartdm_init_port()
1552 rx->pool = dma_pool_create("rx_buffer_pool", uport->dev, in uartdm_init_port()
1554 if (!rx->pool) { in uartdm_init_port()
1556 ret = -ENOMEM; in uartdm_init_port()
1560 rx->buffer = dma_pool_alloc(rx->pool, GFP_KERNEL, &rx->rbuffer); in uartdm_init_port()
1561 if (!rx->buffer) { in uartdm_init_port()
1562 pr_err("%s(): cannot allocate rx->buffer", __func__); in uartdm_init_port()
1563 ret = -ENOMEM; in uartdm_init_port()
1568 rx->command_ptr = kmalloc(sizeof(dmov_box), GFP_KERNEL | __GFP_DMA); in uartdm_init_port()
1569 if (!rx->command_ptr) { in uartdm_init_port()
1570 pr_err("%s(): cannot allocate rx->command_ptr", __func__); in uartdm_init_port()
1571 ret = -ENOMEM; in uartdm_init_port()
1575 rx->command_ptr_ptr = kmalloc(sizeof(u32), GFP_KERNEL | __GFP_DMA); in uartdm_init_port()
1576 if (!rx->command_ptr_ptr) { in uartdm_init_port()
1577 pr_err("%s(): cannot allocate rx->command_ptr_ptr", __func__); in uartdm_init_port()
1578 ret = -ENOMEM; in uartdm_init_port()
1582 rx->command_ptr->num_rows = ((UARTDM_RX_BUF_SIZE >> 4) << 16) | in uartdm_init_port()
1585 rx->command_ptr->dst_row_addr = rx->rbuffer; in uartdm_init_port()
1587 rx->mapped_cmd_ptr = dma_map_single(uport->dev, rx->command_ptr, in uartdm_init_port()
1590 *rx->command_ptr_ptr = CMD_PTR_LP | DMOV_CMD_ADDR(rx->mapped_cmd_ptr); in uartdm_init_port()
1592 rx->cmdptr_dmaaddr = dma_map_single(uport->dev, rx->command_ptr_ptr, in uartdm_init_port()
1594 rx->xfer.cmdptr = DMOV_CMD_ADDR(rx->cmdptr_dmaaddr); in uartdm_init_port()
1596 INIT_WORK(&rx->tty_work, msm_hs_tty_flip_buffer_work); in uartdm_init_port()
1601 kfree(rx->command_ptr); in uartdm_init_port()
1603 dma_pool_free(msm_uport->rx.pool, msm_uport->rx.buffer, in uartdm_init_port()
1604 msm_uport->rx.rbuffer); in uartdm_init_port()
1606 dma_pool_destroy(msm_uport->rx.pool); in uartdm_init_port()
1608 dma_unmap_single(uport->dev, msm_uport->tx.mapped_cmd_ptr_ptr, in uartdm_init_port()
1610 dma_unmap_single(uport->dev, msm_uport->tx.mapped_cmd_ptr, in uartdm_init_port()
1612 kfree(msm_uport->tx.command_ptr_ptr); in uartdm_init_port()
1614 kfree(msm_uport->tx.command_ptr); in uartdm_init_port()
1625 pdev->dev.platform_data; in msm_hs_probe()
1627 if (pdev->id < 0 || pdev->id >= UARTDM_NR) { in msm_hs_probe()
1628 printk(KERN_ERR "Invalid plaform device ID = %d\n", pdev->id); in msm_hs_probe()
1629 return -EINVAL; in msm_hs_probe()
1632 msm_uport = &q_uart_port[pdev->id]; in msm_hs_probe()
1633 uport = &msm_uport->uport; in msm_hs_probe()
1635 uport->dev = &pdev->dev; in msm_hs_probe()
1639 return -ENXIO; in msm_hs_probe()
1641 uport->mapbase = resource->start; in msm_hs_probe()
1642 uport->irq = platform_get_irq(pdev, 0); in msm_hs_probe()
1643 if (unlikely(uport->irq < 0)) in msm_hs_probe()
1644 return -ENXIO; in msm_hs_probe()
1646 if (unlikely(irq_set_irq_wake(uport->irq, 1))) in msm_hs_probe()
1647 return -ENXIO; in msm_hs_probe()
1649 if (pdata == NULL || pdata->rx_wakeup_irq < 0) in msm_hs_probe()
1650 msm_uport->rx_wakeup.irq = -1; in msm_hs_probe()
1652 msm_uport->rx_wakeup.irq = pdata->rx_wakeup_irq; in msm_hs_probe()
1653 msm_uport->rx_wakeup.ignore = 1; in msm_hs_probe()
1654 msm_uport->rx_wakeup.inject_rx = pdata->inject_rx_on_wakeup; in msm_hs_probe()
1655 msm_uport->rx_wakeup.rx_to_inject = pdata->rx_to_inject; in msm_hs_probe()
1657 if (unlikely(msm_uport->rx_wakeup.irq < 0)) in msm_hs_probe()
1658 return -ENXIO; in msm_hs_probe()
1660 if (unlikely(irq_set_irq_wake(msm_uport->rx_wakeup.irq, 1))) in msm_hs_probe()
1661 return -ENXIO; in msm_hs_probe()
1665 msm_uport->exit_lpm_cb = NULL; in msm_hs_probe()
1667 msm_uport->exit_lpm_cb = pdata->exit_lpm_cb; in msm_hs_probe()
1672 return -ENXIO; in msm_hs_probe()
1674 msm_uport->dma_tx_channel = resource->start; in msm_hs_probe()
1675 msm_uport->dma_rx_channel = resource->end; in msm_hs_probe()
1680 return -ENXIO; in msm_hs_probe()
1682 msm_uport->dma_tx_crci = resource->start; in msm_hs_probe()
1683 msm_uport->dma_rx_crci = resource->end; in msm_hs_probe()
1685 uport->iotype = UPIO_MEM; in msm_hs_probe()
1686 uport->fifosize = UART_FIFOSIZE; in msm_hs_probe()
1687 uport->ops = &msm_hs_ops; in msm_hs_probe()
1688 uport->flags = UPF_BOOT_AUTOCONF; in msm_hs_probe()
1689 uport->uartclk = UARTCLK; in msm_hs_probe()
1690 msm_uport->imr_reg = 0x0; in msm_hs_probe()
1691 msm_uport->clk = clk_get(&pdev->dev, "uartdm_clk"); in msm_hs_probe()
1692 if (IS_ERR(msm_uport->clk)) in msm_hs_probe()
1693 return PTR_ERR(msm_uport->clk); in msm_hs_probe()
1699 msm_uport->clk_state = MSM_HS_CLK_PORT_OFF; in msm_hs_probe()
1700 hrtimer_init(&msm_uport->clk_off_timer, CLOCK_MONOTONIC, in msm_hs_probe()
1702 msm_uport->clk_off_timer.function = msm_hs_clk_off_retry; in msm_hs_probe()
1703 msm_uport->clk_off_delay = ktime_set(0, 1000000); /* 1ms */ in msm_hs_probe()
1705 uport->line = pdev->id; in msm_hs_probe()
1713 /* Init all UARTS as non-configured */ in msm_serial_hs_init()
1719 return -ENOMEM; in msm_serial_hs_init()
1745 * - Disables the port
1746 * - Unhook the ISR
1753 BUG_ON(msm_uport->rx.flush < FLUSH_STOP); in msm_hs_shutdown()
1755 spin_lock_irqsave(&uport->lock, flags); in msm_hs_shutdown()
1756 clk_enable(msm_uport->clk); in msm_hs_shutdown()
1763 pm_runtime_disable(uport->dev); in msm_hs_shutdown()
1764 pm_runtime_set_suspended(uport->dev); in msm_hs_shutdown()
1767 free_irq(uport->irq, msm_uport); in msm_hs_shutdown()
1769 free_irq(msm_uport->rx_wakeup.irq, msm_uport); in msm_hs_shutdown()
1771 msm_uport->imr_reg = 0; in msm_hs_shutdown()
1772 msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg); in msm_hs_shutdown()
1774 wait_event(msm_uport->rx.wait, msm_uport->rx.flush == FLUSH_SHUTDOWN); in msm_hs_shutdown()
1776 clk_disable(msm_uport->clk); /* to balance local clk_enable() */ in msm_hs_shutdown()
1777 if (msm_uport->clk_state != MSM_HS_CLK_OFF) in msm_hs_shutdown()
1778 clk_disable(msm_uport->clk); /* to balance clk_state */ in msm_hs_shutdown()
1779 msm_uport->clk_state = MSM_HS_CLK_PORT_OFF; in msm_hs_shutdown()
1781 dma_unmap_single(uport->dev, msm_uport->tx.dma_base, in msm_hs_shutdown()
1784 spin_unlock_irqrestore(&uport->lock, flags); in msm_hs_shutdown()
1786 if (cancel_work_sync(&msm_uport->rx.tty_work)) in msm_hs_shutdown()
1787 msm_hs_tty_flip_buffer_work(&msm_uport->rx.tty_work); in msm_hs_shutdown()
1813 struct msm_hs_port *msm_uport = &q_uart_port[pdev->id]; in msm_hs_runtime_resume()
1815 msm_hs_request_clock_on(&msm_uport->uport); in msm_hs_runtime_resume()
1823 struct msm_hs_port *msm_uport = &q_uart_port[pdev->id]; in msm_hs_runtime_suspend()
1825 msm_hs_request_clock_off(&msm_uport->uport); in msm_hs_runtime_suspend()