Lines Matching +full:rx +full:- +full:tx
2 * Copyright 2007-2010 Analog Devices Inc.
4 * Licensed under the ADI BSD license or the GPL-2 (or later)
17 #define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx …
18 #define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to …
31 #define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint …
32 …844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
33 …844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
34 #define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint …
35 #define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpo…
36 … /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
37 … /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
38 …03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
39 …3858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
40 …3858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
41 …0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
43 … USB_TXCOUNT 0xffc03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
64 #define USB_LINKINFO 0xffc03948 /* Enables programming of some PHY-side dela…
66 #define USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */
67 #define USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */
68 #define USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */
78 #define USB_APHY_CNTRL2 0xffc039e8 /* Register used to prevent re-enumeration o…
89 #define USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0…
91 #define USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0…
92 #define USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpo…
94 …3a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
96 …3a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
97 …errupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
98 … USB_EP_NI0_TXCOUNT 0xffc03a28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
102 #define USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1…
104 #define USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1…
105 #define USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpo…
107 …3a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
109 …3a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
110 …errupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
111 … USB_EP_NI1_TXCOUNT 0xffc03a68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
115 #define USB_EP_NI2_TXMAXP 0xffc03a80 /* Maximum packet size for Host Tx endpoint2…
117 #define USB_EP_NI2_RXMAXP 0xffc03a88 /* Maximum packet size for Host Rx endpoint2…
118 #define USB_EP_NI2_RXCSR 0xffc03a8c /* Control Status register for Host Rx endpo…
120 …3a94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
122 …3a9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
123 …errupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
124 … USB_EP_NI2_TXCOUNT 0xffc03aa8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
128 #define USB_EP_NI3_TXMAXP 0xffc03ac0 /* Maximum packet size for Host Tx endpoint3…
130 #define USB_EP_NI3_RXMAXP 0xffc03ac8 /* Maximum packet size for Host Rx endpoint3…
131 #define USB_EP_NI3_RXCSR 0xffc03acc /* Control Status register for Host Rx endpo…
133 …3ad4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
135 …3adc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
136 …errupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
137 … USB_EP_NI3_TXCOUNT 0xffc03ae8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
141 #define USB_EP_NI4_TXMAXP 0xffc03b00 /* Maximum packet size for Host Tx endpoint4…
143 #define USB_EP_NI4_RXMAXP 0xffc03b08 /* Maximum packet size for Host Rx endpoint4…
144 #define USB_EP_NI4_RXCSR 0xffc03b0c /* Control Status register for Host Rx endpo…
146 …3b14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
148 …3b1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
149 …errupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
150 … USB_EP_NI4_TXCOUNT 0xffc03b28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
154 #define USB_EP_NI5_TXMAXP 0xffc03b40 /* Maximum packet size for Host Tx endpoint5…
156 #define USB_EP_NI5_RXMAXP 0xffc03b48 /* Maximum packet size for Host Rx endpoint5…
157 #define USB_EP_NI5_RXCSR 0xffc03b4c /* Control Status register for Host Rx endpo…
159 …3b54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
161 …3b5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
162 …errupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
163 … USB_EP_NI5_TXCOUNT 0xffc03b68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
167 #define USB_EP_NI6_TXMAXP 0xffc03b80 /* Maximum packet size for Host Tx endpoint6…
169 #define USB_EP_NI6_RXMAXP 0xffc03b88 /* Maximum packet size for Host Rx endpoint6…
170 #define USB_EP_NI6_RXCSR 0xffc03b8c /* Control Status register for Host Rx endpo…
172 …3b94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
174 …3b9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
175 …errupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
176 … USB_EP_NI6_TXCOUNT 0xffc03ba8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
180 #define USB_EP_NI7_TXMAXP 0xffc03bc0 /* Maximum packet size for Host Tx endpoint7…
182 #define USB_EP_NI7_RXMAXP 0xffc03bc8 /* Maximum packet size for Host Rx endpoint7…
183 #define USB_EP_NI7_RXCSR 0xffc03bcc /* Control Status register for Host Rx endpo…
185 …3bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
187 …3bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
188 …errupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
189 … USB_EP_NI7_TXCOUNT 0xffc03be8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
196 #define USB_DMA0ADDRLOW 0xffc03c08 /* Lower 16-bits of memory source/destinatio…
197 #define USB_DMA0ADDRHIGH 0xffc03c0c /* Upper 16-bits of memory source/destinatio…
198 #define USB_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transf…
199 #define USB_DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transf…
204 #define USB_DMA1ADDRLOW 0xffc03c28 /* Lower 16-bits of memory source/destinatio…
205 #define USB_DMA1ADDRHIGH 0xffc03c2c /* Upper 16-bits of memory source/destinatio…
206 #define USB_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transf…
207 #define USB_DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transf…
212 #define USB_DMA2ADDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destinatio…
213 #define USB_DMA2ADDRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destinatio…
214 #define USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transf…
215 #define USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transf…
220 #define USB_DMA3ADDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destinatio…
221 #define USB_DMA3ADDRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destinatio…
222 #define USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transf…
223 #define USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transf…
228 #define USB_DMA4ADDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destinatio…
229 #define USB_DMA4ADDRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destinatio…
230 #define USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transf…
231 #define USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transf…
236 #define USB_DMA5ADDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destinatio…
237 #define USB_DMA5ADDRHIGH 0xffc03cac /* Upper 16-bits of memory source/destinatio…
238 #define USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transf…
239 #define USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transf…
244 #define USB_DMA6ADDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destinatio…
245 #define USB_DMA6ADDRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destinatio…
246 #define USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transf…
247 #define USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transf…
252 #define USB_DMA7ADDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destinatio…
253 #define USB_DMA7ADDRHIGH 0xffc03cec /* Upper 16-bits of memory source/destinatio…
254 #define USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transf…
255 #define USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transf…
282 #define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
284 #define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
286 #define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
288 #define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
290 #define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
292 #define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
294 #define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
296 #define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
301 #define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
303 #define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
305 #define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
307 #define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
309 #define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
311 #define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
313 #define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
320 #define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
322 #define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
324 #define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
326 #define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
328 #define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
330 #define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
332 #define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
337 #define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
339 #define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
341 #define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
343 #define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
345 #define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
347 #define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
349 #define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
443 #define LSDEV 0x20 /* Low-speed indicator */
445 #define FSDEV 0x40 /* Full or High-speed indicator */
551 #define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
566 … TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
576 #define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
592 #define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
613 #define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx F…
622 #define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
631 #define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
668 #define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address…
672 #define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address…
676 #define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DM…
680 #define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DM…