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/qemu/hw/misc/
H A Dallwinner-h3-ccu.c30 REG_PLL_CPUX = 0x0000, /* PLL CPUX Control */
31 REG_PLL_AUDIO = 0x0008, /* PLL Audio Control */
32 REG_PLL_VIDEO = 0x0010, /* PLL Video Control */
33 REG_PLL_VE = 0x0018, /* PLL VE Control */
34 REG_PLL_DDR = 0x0020, /* PLL DDR Control */
35 REG_PLL_PERIPH0 = 0x0028, /* PLL Peripherals 0 Control */
36 REG_PLL_GPU = 0x0038, /* PLL GPU Control */
37 REG_PLL_PERIPH1 = 0x0044, /* PLL Peripherals 1 Control */
38 REG_PLL_DE = 0x0048, /* PLL Display Engine Control */
44 REG_PLL_TIME0 = 0x0200, /* PLL Stable Time 0 */
[all …]
H A Dbcm2835_cprman.c12 * - the PLL channels
17 * multiples sources (usually the xosc, some of the PLL channels and some "test
23 * At each level (PLL, channel and mux), the clock can be altered through
30 * /-->[PLL]-|->[PLL channel]--... [mux]--> to peripherals
31 * | |->[PLL channel] muxes takes [mux]
32 * | \->[PLL channel] inputs from [mux]
34 * [xosc]---|-->[PLL]-|->[PLL channel] and other srcs [mux]
35 * | \->[PLL channel] ...-->[mux]
37 * \-->[PLL]--->[PLL channel] [mux]
54 /* PLL */
[all …]
H A Dstm32l4x5_rcc.c199 * Acknowledge and propagate changes in a PLL frequency.
203 static void pll_update(RccPllState *pll, bool bypass_source) in pll_update() argument
208 /* The common PLLM factor is handled by the PLL mux */ in pll_update()
209 vco_freq = muldiv64(clock_get_hz(pll->in), pll->vco_multiplier, 1); in pll_update()
212 if (!pll->channel_exists[i]) { in pll_update()
216 old_channel_freq = clock_get_hz(pll->channels[i]); in pll_update()
218 !pll->enabled || in pll_update()
219 !pll->channel_enabled[i] || in pll_update()
220 !pll->channel_divider[i]) { in pll_update()
225 pll->channel_divider[i]); in pll_update()
[all …]
H A Dnpcm_clk.c201 #define TYPE_NPCM7XX_CLOCK_PLL "npcm7xx-clock-pll"
217 /* The PLL is grounded if it is not locked yet. */ in npcm7xx_clk_update_pll()
686 NPCM7xxClockPLLState *pll = NPCM7XX_CLOCK_PLL(obj); in npcm7xx_clk_pll_init() local
688 pll->clock_in = qdev_init_clock_in(DEVICE(pll), "clock-in", in npcm7xx_clk_pll_init()
689 npcm7xx_clk_update_pll_cb, pll, in npcm7xx_clk_pll_init()
691 pll->clock_out = qdev_init_clock_out(DEVICE(pll), "clock-out"); in npcm7xx_clk_pll_init()
727 static void npcm7xx_init_clock_pll(NPCM7xxClockPLLState *pll, in npcm7xx_init_clock_pll() argument
730 pll->name = init_info->name; in npcm7xx_init_clock_pll()
731 pll->clk = clk; in npcm7xx_init_clock_pll()
732 pll->reg = init_info->reg; in npcm7xx_init_clock_pll()
[all …]
H A Dsifive_u_prci.c74 /* PLL stays locked */ in sifive_u_prci_write()
81 /* PLL stays locked */ in sifive_u_prci_write()
91 /* PLL stays locked */ in sifive_u_prci_write()
H A Dtrace-events116 msf2_sysreg_write_pll_status(void) "Invalid write to read only PLL status register"
195 …r(uint32_t pll_id, uint32_t old_multiplier, uint32_t new_multiplier) "RCC: PLL %u: vco_multiplier …
196 stm32l4x5_rcc_pll_channel_enable(uint32_t pll_id, uint32_t channel_id) "RCC: PLL %u, channel %u ena…
197 stm32l4x5_rcc_pll_channel_disable(uint32_t pll_id, uint32_t channel_id) "RCC: PLL %u, channel %u di…
198 …id, uint32_t channel_id, uint32_t old_divider, uint32_t new_divider) "RCC: PLL %u, channel %u: div…
199 …channel_id, uint64_t vco_freq, uint64_t old_freq, uint64_t new_freq) "RCC: PLL %d channel %d updat…
H A Dimx_ccm.c46 * Calculate PLL output frequency
H A Dmchp_pfsoc_ioscb.c92 /* All PLL modules in IOSCB have the same register layout */
103 /* PLL is locked */ in mchp_pfsoc_pll_read()
H A Dsifive_e_prci.c63 /* PLL stays locked */ in sifive_e_prci_write()
H A Dzynq_slcr.c205 * return the output frequency of ARM/DDR/IO pll
213 /* first, check if pll is bypassed */ in zynq_slcr_compute_pll()
218 /* is pll disabled ? */ in zynq_slcr_compute_pll()
/qemu/include/hw/misc/
H A Daspeed_scu.h122 * SCU24 H-PLL Parameter Register (for Aspeed AST2400 SOC)
124 * 18 H-PLL parameter selection
125 * 0: Select H-PLL by strapping resistors
126 * 1: Select H-PLL by the programmed registers (SCU24[17:0])
127 * 17 Enable H-PLL bypass mode
128 * 16 Turn off H-PLL
129 * 10:5 H-PLL Numerator
130 * 4 H-PLL Output Divider
131 * 3:0 H-PLL Denumerator
141 * SCU24 H-PLL Parameter Register (for Aspeed AST2500 SOC)
[all …]
H A Dbcm2835_cprman_internals.h15 #define TYPE_CPRMAN_PLL "bcm2835-cprman-pll"
16 #define TYPE_CPRMAN_PLL_CHANNEL "bcm2835-cprman-pll-channel"
112 /* PLL channels */
239 /* PLL init info */
286 CprmanPllState *pll, in set_pll_init_info() argument
289 pll->id = id; in set_pll_init_info()
290 pll->reg_cm = &s->regs[PLL_INIT_INFO[id].cm_offset]; in set_pll_init_info()
291 pll->reg_a2w_ctrl = &s->regs[PLL_INIT_INFO[id].a2w_ctrl_offset]; in set_pll_init_info()
292 pll->reg_a2w_ana = &s->regs[PLL_INIT_INFO[id].a2w_ana_offset]; in set_pll_init_info()
293 pll->prediv_mask = PLL_INIT_INFO[id].prediv_mask; in set_pll_init_info()
[all …]
H A Dstm32l4x5_rcc_internals.h25 #define TYPE_RCC_PLL "stm32l4x5-rcc-pll"
291 /* Pll Channels */
337 /* PLL init info */
350 .name = "pll",
396 static inline void set_pll_init_info(RccPllState *pll, in set_pll_init_info() argument
401 pll->id = id; in set_pll_init_info()
402 pll->vco_multiplier = 1; in set_pll_init_info()
404 pll->channel_enabled[i] = false; in set_pll_init_info()
405 pll->channel_exists[i] = PLL_INIT_INFO[id].channel_exists[i]; in set_pll_init_info()
406 pll->channel_divider[i] = PLL_INIT_INFO[id].default_channel_divider[i]; in set_pll_init_info()
[all …]
H A Dstm32l4x5_rcc.h169 /* Global pll enabled flag */
175 * It should only be set at pll initialization.
H A Dnpcm_clk.h88 * struct NPCM7xxClockPLLState - A PLL module in CLK module.
93 * @reg: The control registers for this PLL module.
H A Dimx_ccm.h19 /* PLL control registers */
/qemu/tests/qtest/
H A Dstm32l4x5_rcc-test.c71 * Update PLL and set MSI as the source clock. in test_init_pll()
82 /* PLL activation */ in test_init_pll()
86 /* Waiting for PLL lock. */ in test_init_pll()
89 /* Switches on the PLL clock source */ in test_init_pll()
143 * PLL has been enabled by previous tests, in test_irq()
174 * (e.g. changing the PLL frequency) are done instantaneously. in main()
H A Dstm32l4x5_usart-test.c125 * Update PLL and set MSI as the source clock. in init_clocks()
136 /* PLL activation */ in init_clocks()
147 /* Switches on the PLL clock source */ in init_clocks()
/qemu/hw/arm/
H A Dvexpress.c413 23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */
416 40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */
H A Dstellaris.c342 /* PLL enable. */ in ssys_write()
354 /* PLL enable. */ in ssys_write()
/qemu/docs/devel/
H A Dclocks.rst11 configuration errors in the clock tree such as badly configured PLL, clock
/qemu/hw/sh4/
H A Dsh7750_regs.h355 #define SH7750_FRQCR_PLL1EN 0x0400 /* PLL circuit 1 enable */
356 #define SH7750_FRQCR_PLL2EN 0x0200 /* PLL circuit 2 enable */
/qemu/linux-user/
H A Dsyscall_defs.h283 abi_long constant; /* PLL (phase-locked loop) time constant */
313 abi_llong constant; /* PLL (phase-locked loop) time constant */
/qemu/hw/char/
H A Descc.c306 /* PLL disabled */ in escc_soft_reset_chn()
/qemu/tests/data/qobject/
H A Dqdict.txt4945 dvb-pll.c: 17175
4946 dvb-pll.h: 1617

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