199  * Acknowledge and propagate changes in a PLL frequency.
203 static void pll_update(RccPllState *pll, bool bypass_source)  in pll_update()  argument
208     /* The common PLLM factor is handled by the PLL mux */  in pll_update()
209     vco_freq = muldiv64(clock_get_hz(pll->in), pll->vco_multiplier, 1);  in pll_update()
212         if (!pll->channel_exists[i]) {  in pll_update()
216         old_channel_freq = clock_get_hz(pll->channels[i]);  in pll_update()
218             !pll->enabled ||  in pll_update()
219             !pll->channel_enabled[i] ||  in pll_update()
220             !pll->channel_divider[i]) {  in pll_update()
225                                     pll->channel_divider[i]);  in pll_update()
233         clock_update_hz(pll->channels[i], channel_freq);  in pll_update()
234         trace_stm32l4x5_rcc_pll_update(pll->id, i, vco_freq,  in pll_update()
311 static void pll_set_vco_multiplier(RccPllState *pll, uint32_t vco_multiplier)  in pll_set_vco_multiplier()  argument
313     if (pll->vco_multiplier == vco_multiplier) {  in pll_set_vco_multiplier()
319             "%s: VCO multiplier is out of bound (%u) for PLL %u\n",  in pll_set_vco_multiplier()
320             __func__, vco_multiplier, pll->id);  in pll_set_vco_multiplier()
324     trace_stm32l4x5_rcc_pll_set_vco_multiplier(pll->id,  in pll_set_vco_multiplier()
325         pll->vco_multiplier, vco_multiplier);  in pll_set_vco_multiplier()
327     pll->vco_multiplier = vco_multiplier;  in pll_set_vco_multiplier()
328     pll_update(pll, false);  in pll_set_vco_multiplier()
331 static void pll_set_enable(RccPllState *pll, bool enabled)  in pll_set_enable()  argument
333     if (pll->enabled == enabled) {  in pll_set_enable()
337     pll->enabled = enabled;  in pll_set_enable()
338     pll_update(pll, false);  in pll_set_enable()
341 static void pll_set_channel_enable(RccPllState *pll,  in pll_set_channel_enable()  argument
345     if (pll->channel_enabled[channel] == enabled) {  in pll_set_channel_enable()
350         trace_stm32l4x5_rcc_pll_channel_enable(pll->id, channel);  in pll_set_channel_enable()
352         trace_stm32l4x5_rcc_pll_channel_disable(pll->id, channel);  in pll_set_channel_enable()
355     pll->channel_enabled[channel] = enabled;  in pll_set_channel_enable()
356     pll_update(pll, false);  in pll_set_channel_enable()
359 static void pll_set_channel_divider(RccPllState *pll,  in pll_set_channel_divider()  argument
363     if (pll->channel_divider[channel] == divider) {  in pll_set_channel_divider()
367     trace_stm32l4x5_rcc_pll_set_channel_divider(pll->id,  in pll_set_channel_divider()
368         channel, pll->channel_divider[channel], divider);  in pll_set_channel_divider()
370     pll->channel_divider[channel] = divider;  in pll_set_channel_divider()
371     pll_update(pll, false);  in pll_set_channel_divider()
448      * PLLON cannot be reset if the PLL clock is used as the system clock.  in rcc_update_cr_register()
760                       "%s: Invalid PLL ID: %u\n", __func__, pll_id);  in rcc_update_pllsaixcfgr()
1404         RccPllState *pll = &s->plls[i];  in stm32l4x5_rcc_realize()  local
1406         clock_set_source(pll->in, s->clock_muxes[RCC_CLOCK_MUX_PLL_INPUT].out);  in stm32l4x5_rcc_realize()
1408         if (!qdev_realize(DEVICE(pll), NULL, errp)) {  in stm32l4x5_rcc_realize()