15 #define TYPE_CPRMAN_PLL "bcm2835-cprman-pll"
16 #define TYPE_CPRMAN_PLL_CHANNEL "bcm2835-cprman-pll-channel"
112 /* PLL channels */
239 /* PLL init info */
286                                      CprmanPllState *pll,  in set_pll_init_info()  argument
289     pll->id = id;  in set_pll_init_info()
290     pll->reg_cm = &s->regs[PLL_INIT_INFO[id].cm_offset];  in set_pll_init_info()
291     pll->reg_a2w_ctrl = &s->regs[PLL_INIT_INFO[id].a2w_ctrl_offset];  in set_pll_init_info()
292     pll->reg_a2w_ana = &s->regs[PLL_INIT_INFO[id].a2w_ana_offset];  in set_pll_init_info()
293     pll->prediv_mask = PLL_INIT_INFO[id].prediv_mask;  in set_pll_init_info()
294     pll->reg_a2w_frac = &s->regs[PLL_INIT_INFO[id].a2w_frac_offset];  in set_pll_init_info()
298 /* PLL channel init info */
438         CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll a */        \
439         CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll c */        \
440         CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll d */        \
441         CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll h */        \
442         CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll c, core1 */ \
443         CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll c, core2 */ \
461 /* All the PLL "core" channels */
476 /* All the PLL "per" channels */
492  * The DSI0 channels. This one got an intermediate mux between the PLL channels
803      * Even though a PLL channel has a CM register, it shares it with its
804      * parent PLL. The parent already takes care of the reset value.