Lines Matching full:pll

12  *   - the PLL channels
17 * multiples sources (usually the xosc, some of the PLL channels and some "test
23 * At each level (PLL, channel and mux), the clock can be altered through
30 * /-->[PLL]-|->[PLL channel]--... [mux]--> to peripherals
31 * | |->[PLL channel] muxes takes [mux]
32 * | \->[PLL channel] inputs from [mux]
34 * [xosc]---|-->[PLL]-|->[PLL channel] and other srcs [mux]
35 * | \->[PLL channel] ...-->[mux]
37 * \-->[PLL]--->[PLL channel] [mux]
54 /* PLL */
67 static bool pll_is_locked(const CprmanPllState *pll) in pll_is_locked() argument
69 return !FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, PWRDN) in pll_is_locked()
70 && !FIELD_EX32(*pll->reg_cm, CM_PLLx, ANARST); in pll_is_locked()
73 static void pll_update(CprmanPllState *pll) in pll_update() argument
77 if (!pll_is_locked(pll)) { in pll_update()
78 clock_update(pll->out, 0); in pll_update()
82 pdiv = FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, PDIV); in pll_update()
85 clock_update(pll->out, 0); in pll_update()
89 ndiv = FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, NDIV); in pll_update()
90 fdiv = FIELD_EX32(*pll->reg_a2w_frac, A2W_PLLx_FRAC, FRAC); in pll_update()
92 if (pll->reg_a2w_ana[1] & pll->prediv_mask) { in pll_update()
102 freq = clock_get_hz(pll->xosc_in) * in pll_update()
107 clock_update_hz(pll->out, freq); in pll_update()
153 /* PLL channel */
199 /* Update a PLL and all its channels */
201 CprmanPllState *pll) in pll_update_all_channels() argument
205 pll_update(pll); in pll_update_all_channels()
209 if (channel->parent == pll->id) { in pll_update_all_channels()
224 s->pll_in = qdev_init_clock_in(DEVICE(s), "pll-in", in pll_channel_init()
547 * A given CM_PLLx register is shared by both the PLL and the channels in cprman_write()
548 * of this PLL. in cprman_write()
738 CprmanPllState *pll = &s->plls[i]; in cprman_realize() local
740 clock_set_source(pll->xosc_in, s->xosc); in cprman_realize()
742 if (!qdev_realize(DEVICE(pll), NULL, errp)) { in cprman_realize()