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/linux-3.3/drivers/spi/
Dspi-ppc4xx.c38 #include <linux/gpio.h>
44 #include <asm/dcr-regs.h>
46 /* bits in mode register - bit 0 is MSb */
59 * SPI_PPC4XX_MODE_RD = 0 means "MSB first" - this is the normal mode
60 * SPI_PPC4XX_MODE_RD = 1 means "LSB first" - this is bit-reversed mode
108 * CDM = (OPBCLK/4*SCPClkOut) - 1
150 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", in spi_ppc4xx_txrx()
151 t->tx_buf, t->rx_buf, t->len); in spi_ppc4xx_txrx()
153 hw = spi_master_get_devdata(spi->master); in spi_ppc4xx_txrx()
155 hw->tx = t->tx_buf; in spi_ppc4xx_txrx()
[all …]
Dspi-gpio.c2 * SPI master driver using generic bitbanged GPIO
24 #include <linux/gpio.h>
37 * platform_device->driver_data ... points to spi_gpio
39 * spi->controller_state ... reserved for bitbang framework code
40 * spi->controller_data ... holds chipselect GPIO
42 * spi->master->dev.driver_data ... points to spi_gpio->bitbang
51 /*----------------------------------------------------------------------*/
54 * Because the overhead of going through four GPIO procedure calls
58 * - The slow generic way: set up platform_data to hold the GPIO
62 * - The quicker inlined way: only helps with platform GPIO code
[all …]
Dspi-fsl-spi.c28 #include <linux/dma-mapping.h>
33 #include <linux/gpio.h>
40 #include "spi-fsl-lib.h"
77 * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
105 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master); in fsl_spi_change_mode()
106 struct spi_mpc8xxx_cs *cs = spi->controller_state; in fsl_spi_change_mode() local
107 struct fsl_spi_reg *reg_base = mspi->reg_base; in fsl_spi_change_mode()
108 __be32 __iomem *mode = &reg_base->mode; in fsl_spi_change_mode()
111 if (cs->hw_mode == mpc8xxx_spi_read_reg(mode)) in fsl_spi_change_mode()
118 mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE); in fsl_spi_change_mode()
[all …]
Dspi-imx.c2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
18 * Boston, MA 02110-1301, USA.
25 #include <linux/gpio.h>
59 u8 cs; member
104 return d->devtype_data->devtype == IMX27_CSPI; in is_imx27_cspi()
109 return d->devtype_data->devtype == IMX35_CSPI; in is_imx35_cspi()
114 return (d->devtype_data->devtype == IMX51_ECSPI) ? 64 : 8; in spi_imx_get_fifosize()
120 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
122 if (spi_imx->rx_buf) { \
123 *(type *)spi_imx->rx_buf = val; \
[all …]
Dspi-s3c24xx.c3 * Copyright 2006-2009 Simtec Electronics
21 #include <linux/gpio.h>
29 #include <plat/regs-spi.h>
35 #include "spi-s3c24xx-fiq.h"
38 * s3c24xx_spi_devstate - per device data
74 int cs, int pol);
94 return spi_master_get_devdata(sdev->master); in to_hw()
97 static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol) in s3c24xx_spi_gpiocs() argument
99 gpio_set_value(spi->pin_cs, pol); in s3c24xx_spi_gpiocs()
104 struct s3c24xx_spi_devstate *cs = spi->controller_state; in s3c24xx_spi_chipsel() local
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Dspi-bitbang.c16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
33 /*----------------------------------------------------------------------*/
36 * FIRST PART (OPTIONAL): word-at-a-time spi_transfer support.
37 * Use this for GPIO or shift-register level hardware APIs.
39 * spi_bitbang_cs is in spi_device->controller_state, which is unavailable
41 * used, though maybe they're called from controller-aware code.
43 * chipselect() and friends may use use spi_device->controller_data and
47 * NOTE: SPI controller pins can often be used as GPIO pins instead,
72 unsigned bits = t->bits_per_word ? : spi->bits_per_word; in bitbang_txrx_8()
73 unsigned count = t->len; in bitbang_txrx_8()
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/linux-3.3/arch/arm/mach-omap2/
Dboard-igep0020.c4 * Modified from mach-omap2/board-generic.c
18 #include <linux/gpio.h>
27 #include <asm/mach-types.h>
35 #include <video/omap-panel-dvi.h>
40 #include "sdram-numonyx-m65kxxxxam.h"
41 #include "common-board-devices.h"
66 * --------------------------------------------------------------------------
68 * --------------------------------------------------------------------------
69 * | 0 | B | high | gpio94 | gpio95 | - |
70 * | 0 | B/C (B-compatible) | high | gpio94 | gpio95 | gpio137 |
[all …]
Dcommon-board-devices.c2 * common-board-devices.c
19 * 02110-1301 USA
23 #include <linux/gpio.h>
30 #include "common-board-devices.h"
47 .gpio_pendown = -EINVAL,
53 .bus_num = -EINVAL,
57 .irq = -EINVAL,
67 if (board_pdata && board_pdata->get_pendown_state) { in omap_ads7846_init()
70 pr_err("Couldn't obtain gpio for TSPenDown: %d\n", err); in omap_ads7846_init()
81 spi_bi->bus_num = bus_num; in omap_ads7846_init()
[all …]
Dboard-cm-t3517.c2 * linux/arch/arm/mach-omap2/board-cm-t3517.c
4 * Support for the CompuLab CM-T3517 modules
21 * 02110-1301 USA
29 #include <linux/gpio.h>
31 #include <linux/rtc-v3020.h>
37 #include <asm/mach-types.h>
51 #include "common-board-devices.h"
56 .gpio = 186,
57 .name = "cm-t3517:green",
69 .name = "leds-gpio",
[all …]
Dgpmc-smsc911x.c2 * linux/arch/arm/mach-omap2/gpmc-smsc911x.c
4 * Copyright (C) 2009 Li-Pro.Net
5 * Stephan Linz <linz@li-pro.net>
7 * Modified from linux/arch/arm/mach-omap2/gpmc-smc91x.c
17 #include <linux/gpio.h>
27 #include <plat/gpmc-smsc911x.h>
69 .gpio = -EINVAL,
78 * with other reg-fixed-voltage devices. The real fix should
84 .name = "reg-fixed-voltage",
93 * assume that pin multiplexing is done in the board-*.c file,
[all …]
Dboard-zoom-debugboard.c12 #include <linux/gpio.h>
18 #include <plat/gpmc-smsc911x.h>
20 #include <mach/board-zoom.h>
32 .cs = ZOOM_SMSC911X_CS,
34 .gpio_reset = -EINVAL,
73 "TL16CP754C GPIO") < 0) { in zoom_init_quaduart()
74 pr_err("Failed to request GPIO%d for TL16CP754C\n", in zoom_init_quaduart()
89 if (gpio_request_one(quart_gpio, GPIOF_IN, "TL16CP754C GPIO") < 0) in zoom_init_quaduart()
90 printk(KERN_ERR "Failed to request GPIO%d for TL16CP754C\n", in zoom_init_quaduart()
103 printk(KERN_ERR "Failed to request GPIO%d for Zoom debug" in omap_zoom_debugboard_detect()
Dboard-3430sdp.c2 * linux/arch/arm/mach-omap2/board-3430sdp.c
6 * Modified from mach-omap2/board-generic.c
25 #include <linux/gpio.h>
29 #include <asm/mach-types.h>
40 #include <video/omap-panel-dvi.h>
42 #include <plat/gpmc-smc91x.h>
44 #include "board-flash.h"
46 #include "sdram-qimonda-hyb18m512160af-6.h"
50 #include "common-board-devices.h"
111 static struct gpio sdp3430_dss_gpios[] __initdata = {
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/linux-3.3/arch/m68k/include/asm/
Dm5249sim.h4 * m5249sim.h -- ColdFire 5249 System Integration Module support.
51 #define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
52 #define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
53 #define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */
54 #define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
55 #define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
56 #define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
57 #define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
58 #define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
59 #define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
[all …]
Dm5407sim.h4 * m5407sim.h -- ColdFire 5407 System Integration Module support.
50 #define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
51 #define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
52 #define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */
53 #define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
54 #define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
55 #define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
57 #define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
58 #define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
59 #define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
[all …]
Dm5206sim.h4 * m5206sim.h -- ColdFire 5206 System Integration Module support.
61 #define MCFSIM_CSAR0 0x64 /* CS 0 Address 0 reg (r/w) */
62 #define MCFSIM_CSMR0 0x68 /* CS 0 Mask 0 reg (r/w) */
63 #define MCFSIM_CSCR0 0x6e /* CS 0 Control reg (r/w) */
64 #define MCFSIM_CSAR1 0x70 /* CS 1 Address reg (r/w) */
65 #define MCFSIM_CSMR1 0x74 /* CS 1 Mask reg (r/w) */
66 #define MCFSIM_CSCR1 0x7a /* CS 1 Control reg (r/w) */
67 #define MCFSIM_CSAR2 0x7c /* CS 2 Address reg (r/w) */
68 #define MCFSIM_CSMR2 0x80 /* CS 2 Mask reg (r/w) */
69 #define MCFSIM_CSCR2 0x86 /* CS 2 Control reg (r/w) */
[all …]
/linux-3.3/arch/arm/mach-u300/
Dspi.c2 * arch/arm/mach-u300/spi.c
4 * Copyright (C) 2009 ST-Ericsson AB
23 pr_debug("CORE: %s called with CS=0x%x (%s)\n", in select_dummy_chip()
28 * Here you would write the chip select value to the GPIO pins if in select_dummy_chip()
47 * This is where you insert a call to a function to enable CS
48 * (usually GPIO) for a certain chip.
58 .modalias = "spi-dummy",
63 /* .irq - no external IRQ routed from this device */
67 /* Means SPI_CS_HIGH, change if e.g low CS */
77 * On the APP CPU GPIO 4, 5 and 6 are connected as generic
[all …]
/linux-3.3/Documentation/blackfin/
Dbfin-spi-notes.txt3 With the Blackfin on-chip SPI peripheral, there is some logic tied to the CPHA
7 the entire SPI transfer. - And not just bits_per_word duration.
9 In most cases you can utilize SPI MODE_3 instead of MODE_0 to work-around this
11 timing, you can utilize the GPIO controlled SPI Slave Select option instead.
12 In this case, you should use GPIO based CS for all of your slaves and not just
13 the ones using mode 0 or 2 in order to guarantee correct CS toggling behavior.
16 but use it as a GPIO instead.
/linux-3.3/arch/arm/mach-sa1100/
Dh3xxx.c14 #include <linux/gpio.h>
17 #include <linux/mfd/htc-egpio.h>
33 while (n--) { in h3xxx_init_gpio()
34 const char *name = s->name; in h3xxx_init_gpio()
39 err = gpio_request(s->gpio, name); in h3xxx_init_gpio()
41 printk(KERN_ERR "gpio%u: unable to request: %d\n", in h3xxx_init_gpio()
42 s->gpio, err); in h3xxx_init_gpio()
45 if (s->mode >= 0) { in h3xxx_init_gpio()
46 err = gpio_direction_output(s->gpio, s->mode); in h3xxx_init_gpio()
48 err = gpio_direction_input(s->gpio); in h3xxx_init_gpio()
[all …]
/linux-3.3/arch/arm/mach-s3c2410/include/mach/
Dspi.h1 /* arch/arm/mach-s3c2410/include/mach/spi.h
6 * S3C2410 - SPI Controller platform_device info
17 int pin_cs; /* simple gpio cs */
24 void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol);
27 /* Standard setup / suspend routines for SPI GPIO pins. */
/linux-3.3/arch/arm/mach-davinci/
Dboard-tnetv107x-evm.c18 #include <linux/dma-mapping.h>
20 #include <linux/gpio.h>
31 #include <asm/mach-types.h>
43 static int initialize_gpio(int gpio, char *desc) in initialize_gpio() argument
47 ret = gpio_request(gpio, desc); in initialize_gpio()
49 pr_err_ratelimited("cannot open %s gpio\n", desc); in initialize_gpio()
50 return -ENOSYS; in initialize_gpio()
52 gpio_direction_input(gpio); in initialize_gpio()
53 return gpio; in initialize_gpio()
58 static int gpio; in mmc_get_cd() local
[all …]
/linux-3.3/arch/mips/bcm63xx/
Ddev-pcmcia.c69 static int __init config_pcmcia_cs(unsigned int cs, in config_pcmcia_cs() argument
74 ret = bcm63xx_set_cs_status(cs, 0); in config_pcmcia_cs()
76 ret = bcm63xx_set_cs_base(cs, base, size); in config_pcmcia_cs()
78 ret = bcm63xx_set_cs_status(cs, 1); in config_pcmcia_cs()
83 unsigned int cs; member
88 .cs = MPI_CS_PCMCIA_COMMON,
93 .cs = MPI_CS_PCMCIA_ATTR,
98 .cs = MPI_CS_PCMCIA_IO,
111 /* use correct pcmcia ready gpio depending on processor */ in bcm63xx_pcmcia_register()
122 return -ENODEV; in bcm63xx_pcmcia_register()
[all …]
/linux-3.3/Documentation/devicetree/bindings/spi/
Dfsl-imx-cspi.txt5 - compatible : Should be "fsl,<soc>-cspi" or "fsl,<soc>-ecspi"
6 - reg : Offset and length of the register set for the device
7 - interrupts : Should contain CSPI/eCSPI interrupt
8 - fsl,spi-num-chipselects : Contains the number of the chipselect
9 - cs-gpios : Specifies the gpio pins to be used for chipselects.
14 #address-cells = <1>;
15 #size-cells = <0>;
16 compatible = "fsl,imx51-ecspi";
19 fsl,spi-num-chipselects = <2>;
20 cs-gpios = <&gpio3 24 0>, /* GPIO4_24 */
/linux-3.3/arch/arm/plat-samsung/include/plat/
Ds3c64xx-spi.h1 /* linux/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
17 * struct s3c64xx_spi_csinfo - ChipSelect description
20 * @line: Custom 'identity' of the CS line.
21 * @set_level: CS line control.
23 * This is per SPI-Slave Chipselect information.
34 * struct s3c64xx_spi_info - SPI Controller defining structure
37 * by the platform's clock-management-unit and not in SPI controller.
38 * @num_cs: Number of CS this controller emulates.
40 * @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6
61 * s3c64xx_spi_set_platdata - SPI Controller configure callback by the board
[all …]
/linux-3.3/arch/arm/mach-netx/include/mach/
Dnetx-regs.h2 * arch/arm/mach-netx/include/mach/netx-regs.h
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
184 * GPIO and timer module *
189 #define NETX_GPIO_CFG(gpio) NETX_GPIO_REG(0x0 + ((gpio)<<2)) argument
190 #define NETX_GPIO_THRESHOLD_CAPTURE(gpio) NETX_GPIO_REG(0x40 + ((gpio)<<2)) argument
225 #define GPIO_BIT(gpio) (1<<(gpio)) argument
338 #define NETX_MEMCR_SRAM_CTRL(cs) NETX_MEMCR_REG(0x0 + 4 * (cs)) /* SRAM for CS 0..2 */ argument
364 #define NETX_DPMAS_EXT_CONFIG(cs) NETX_DPMAS_REG(0x610 + 4 * (cs)) argument
/linux-3.3/arch/arm/mach-imx/
Dmach-armadillo5x0.c23 * MA 02110-1301, USA.
30 #include <linux/gpio.h>
43 #include <asm/mach-types.h>
50 #include <mach/iomux-mx3.h>
53 #include "devices-imx31.h"
54 #include "crmregs-imx31.h"
159 err = gpio_request(OTG_RESET, "USB-OTG-RESET"); in usbotg_init()
161 pr_err("Failed to request the usb otg reset gpio\n"); in usbotg_init()
176 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED | in usbotg_init()
205 err = gpio_request(USBH2_CS, "USB-H2-CS"); in usbh2_init()
[all …]

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