Lines Matching +full:cs +full:- +full:gpio
4 * m5206sim.h -- ColdFire 5206 System Integration Module support.
61 #define MCFSIM_CSAR0 0x64 /* CS 0 Address 0 reg (r/w) */
62 #define MCFSIM_CSMR0 0x68 /* CS 0 Mask 0 reg (r/w) */
63 #define MCFSIM_CSCR0 0x6e /* CS 0 Control reg (r/w) */
64 #define MCFSIM_CSAR1 0x70 /* CS 1 Address reg (r/w) */
65 #define MCFSIM_CSMR1 0x74 /* CS 1 Mask reg (r/w) */
66 #define MCFSIM_CSCR1 0x7a /* CS 1 Control reg (r/w) */
67 #define MCFSIM_CSAR2 0x7c /* CS 2 Address reg (r/w) */
68 #define MCFSIM_CSMR2 0x80 /* CS 2 Mask reg (r/w) */
69 #define MCFSIM_CSCR2 0x86 /* CS 2 Control reg (r/w) */
70 #define MCFSIM_CSAR3 0x88 /* CS 3 Address reg (r/w) */
71 #define MCFSIM_CSMR3 0x8c /* CS 3 Mask reg (r/w) */
72 #define MCFSIM_CSCR3 0x92 /* CS 3 Control reg (r/w) */
73 #define MCFSIM_CSAR4 0x94 /* CS 4 Address reg (r/w) */
74 #define MCFSIM_CSMR4 0x98 /* CS 4 Mask reg (r/w) */
75 #define MCFSIM_CSCR4 0x9e /* CS 4 Control reg (r/w) */
76 #define MCFSIM_CSAR5 0xa0 /* CS 5 Address reg (r/w) */
77 #define MCFSIM_CSMR5 0xa4 /* CS 5 Mask reg (r/w) */
78 #define MCFSIM_CSCR5 0xaa /* CS 5 Control reg (r/w) */
79 #define MCFSIM_CSAR6 0xac /* CS 6 Address reg (r/w) */
80 #define MCFSIM_CSMR6 0xb0 /* CS 6 Mask reg (r/w) */
81 #define MCFSIM_CSCR6 0xb6 /* CS 6 Control reg (r/w) */
82 #define MCFSIM_CSAR7 0xb8 /* CS 7 Address reg (r/w) */
83 #define MCFSIM_CSMR7 0xbc /* CS 7 Mask reg (r/w) */
84 #define MCFSIM_CSCR7 0xc2 /* CS 7 Control reg (r/w) */
117 * Generic GPIO
120 #define MCFGPIO_IRQ_VECBASE -1
121 #define MCFGPIO_IRQ_MAX -1