1 /*
2 * linux/arch/arm/mach-omap2/board-3430sdp.c
3 *
4 * Copyright (C) 2007 Texas Instruments
5 *
6 * Modified from mach-omap2/board-generic.c
7 *
8 * Initial code: Syed Mohammed Khasim
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/platform_device.h>
18 #include <linux/delay.h>
19 #include <linux/input.h>
20 #include <linux/input/matrix_keypad.h>
21 #include <linux/spi/spi.h>
22 #include <linux/i2c/twl.h>
23 #include <linux/regulator/machine.h>
24 #include <linux/io.h>
25 #include <linux/gpio.h>
26 #include <linux/mmc/host.h>
27
28 #include <mach/hardware.h>
29 #include <asm/mach-types.h>
30 #include <asm/mach/arch.h>
31 #include <asm/mach/map.h>
32
33 #include <plat/mcspi.h>
34 #include <plat/board.h>
35 #include <plat/usb.h>
36 #include "common.h"
37 #include <plat/dma.h>
38 #include <plat/gpmc.h>
39 #include <video/omapdss.h>
40 #include <video/omap-panel-dvi.h>
41
42 #include <plat/gpmc-smc91x.h>
43
44 #include "board-flash.h"
45 #include "mux.h"
46 #include "sdram-qimonda-hyb18m512160af-6.h"
47 #include "hsmmc.h"
48 #include "pm.h"
49 #include "control.h"
50 #include "common-board-devices.h"
51
52 #define CONFIG_DISABLE_HFCLK 1
53
54 #define SDP3430_TS_GPIO_IRQ_SDPV1 3
55 #define SDP3430_TS_GPIO_IRQ_SDPV2 2
56
57 #define ENABLE_VAUX3_DEDICATED 0x03
58 #define ENABLE_VAUX3_DEV_GRP 0x20
59
60 #define TWL4030_MSECURE_GPIO 22
61
62 static uint32_t board_keymap[] = {
63 KEY(0, 0, KEY_LEFT),
64 KEY(0, 1, KEY_RIGHT),
65 KEY(0, 2, KEY_A),
66 KEY(0, 3, KEY_B),
67 KEY(0, 4, KEY_C),
68 KEY(1, 0, KEY_DOWN),
69 KEY(1, 1, KEY_UP),
70 KEY(1, 2, KEY_E),
71 KEY(1, 3, KEY_F),
72 KEY(1, 4, KEY_G),
73 KEY(2, 0, KEY_ENTER),
74 KEY(2, 1, KEY_I),
75 KEY(2, 2, KEY_J),
76 KEY(2, 3, KEY_K),
77 KEY(2, 4, KEY_3),
78 KEY(3, 0, KEY_M),
79 KEY(3, 1, KEY_N),
80 KEY(3, 2, KEY_O),
81 KEY(3, 3, KEY_P),
82 KEY(3, 4, KEY_Q),
83 KEY(4, 0, KEY_R),
84 KEY(4, 1, KEY_4),
85 KEY(4, 2, KEY_T),
86 KEY(4, 3, KEY_U),
87 KEY(4, 4, KEY_D),
88 KEY(5, 0, KEY_V),
89 KEY(5, 1, KEY_W),
90 KEY(5, 2, KEY_L),
91 KEY(5, 3, KEY_S),
92 KEY(5, 4, KEY_H),
93 0
94 };
95
96 static struct matrix_keymap_data board_map_data = {
97 .keymap = board_keymap,
98 .keymap_size = ARRAY_SIZE(board_keymap),
99 };
100
101 static struct twl4030_keypad_data sdp3430_kp_data = {
102 .keymap_data = &board_map_data,
103 .rows = 5,
104 .cols = 6,
105 .rep = 1,
106 };
107
108 #define SDP3430_LCD_PANEL_BACKLIGHT_GPIO 8
109 #define SDP3430_LCD_PANEL_ENABLE_GPIO 5
110
111 static struct gpio sdp3430_dss_gpios[] __initdata = {
112 {SDP3430_LCD_PANEL_ENABLE_GPIO, GPIOF_OUT_INIT_LOW, "LCD reset" },
113 {SDP3430_LCD_PANEL_BACKLIGHT_GPIO, GPIOF_OUT_INIT_LOW, "LCD Backlight"},
114 };
115
116 static int lcd_enabled;
117 static int dvi_enabled;
118
sdp3430_display_init(void)119 static void __init sdp3430_display_init(void)
120 {
121 int r;
122
123 r = gpio_request_array(sdp3430_dss_gpios,
124 ARRAY_SIZE(sdp3430_dss_gpios));
125 if (r)
126 printk(KERN_ERR "failed to get LCD control GPIOs\n");
127
128 }
129
sdp3430_panel_enable_lcd(struct omap_dss_device * dssdev)130 static int sdp3430_panel_enable_lcd(struct omap_dss_device *dssdev)
131 {
132 if (dvi_enabled) {
133 printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
134 return -EINVAL;
135 }
136
137 gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 1);
138 gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 1);
139
140 lcd_enabled = 1;
141
142 return 0;
143 }
144
sdp3430_panel_disable_lcd(struct omap_dss_device * dssdev)145 static void sdp3430_panel_disable_lcd(struct omap_dss_device *dssdev)
146 {
147 lcd_enabled = 0;
148
149 gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 0);
150 gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 0);
151 }
152
sdp3430_panel_enable_dvi(struct omap_dss_device * dssdev)153 static int sdp3430_panel_enable_dvi(struct omap_dss_device *dssdev)
154 {
155 if (lcd_enabled) {
156 printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
157 return -EINVAL;
158 }
159
160 dvi_enabled = 1;
161
162 return 0;
163 }
164
sdp3430_panel_disable_dvi(struct omap_dss_device * dssdev)165 static void sdp3430_panel_disable_dvi(struct omap_dss_device *dssdev)
166 {
167 dvi_enabled = 0;
168 }
169
sdp3430_panel_enable_tv(struct omap_dss_device * dssdev)170 static int sdp3430_panel_enable_tv(struct omap_dss_device *dssdev)
171 {
172 return 0;
173 }
174
sdp3430_panel_disable_tv(struct omap_dss_device * dssdev)175 static void sdp3430_panel_disable_tv(struct omap_dss_device *dssdev)
176 {
177 }
178
179
180 static struct omap_dss_device sdp3430_lcd_device = {
181 .name = "lcd",
182 .driver_name = "sharp_ls_panel",
183 .type = OMAP_DISPLAY_TYPE_DPI,
184 .phy.dpi.data_lines = 16,
185 .platform_enable = sdp3430_panel_enable_lcd,
186 .platform_disable = sdp3430_panel_disable_lcd,
187 };
188
189 static struct panel_dvi_platform_data dvi_panel = {
190 .platform_enable = sdp3430_panel_enable_dvi,
191 .platform_disable = sdp3430_panel_disable_dvi,
192 };
193
194 static struct omap_dss_device sdp3430_dvi_device = {
195 .name = "dvi",
196 .type = OMAP_DISPLAY_TYPE_DPI,
197 .driver_name = "dvi",
198 .data = &dvi_panel,
199 .phy.dpi.data_lines = 24,
200 };
201
202 static struct omap_dss_device sdp3430_tv_device = {
203 .name = "tv",
204 .driver_name = "venc",
205 .type = OMAP_DISPLAY_TYPE_VENC,
206 .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
207 .platform_enable = sdp3430_panel_enable_tv,
208 .platform_disable = sdp3430_panel_disable_tv,
209 };
210
211
212 static struct omap_dss_device *sdp3430_dss_devices[] = {
213 &sdp3430_lcd_device,
214 &sdp3430_dvi_device,
215 &sdp3430_tv_device,
216 };
217
218 static struct omap_dss_board_info sdp3430_dss_data = {
219 .num_devices = ARRAY_SIZE(sdp3430_dss_devices),
220 .devices = sdp3430_dss_devices,
221 .default_device = &sdp3430_lcd_device,
222 };
223
224 static struct omap_board_config_kernel sdp3430_config[] __initdata = {
225 };
226
227 static struct omap2_hsmmc_info mmc[] = {
228 {
229 .mmc = 1,
230 /* 8 bits (default) requires S6.3 == ON,
231 * so the SIM card isn't used; else 4 bits.
232 */
233 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
234 .gpio_wp = 4,
235 },
236 {
237 .mmc = 2,
238 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
239 .gpio_wp = 7,
240 },
241 {} /* Terminator */
242 };
243
sdp3430_twl_gpio_setup(struct device * dev,unsigned gpio,unsigned ngpio)244 static int sdp3430_twl_gpio_setup(struct device *dev,
245 unsigned gpio, unsigned ngpio)
246 {
247 /* gpio + 0 is "mmc0_cd" (input/IRQ),
248 * gpio + 1 is "mmc1_cd" (input/IRQ)
249 */
250 mmc[0].gpio_cd = gpio + 0;
251 mmc[1].gpio_cd = gpio + 1;
252 omap2_hsmmc_init(mmc);
253
254 /* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */
255 gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "sub_lcd_en_bkl");
256
257 /* gpio + 15 is "sub_lcd_nRST" (output) */
258 gpio_request_one(gpio + 15, GPIOF_OUT_INIT_LOW, "sub_lcd_nRST");
259
260 return 0;
261 }
262
263 static struct twl4030_gpio_platform_data sdp3430_gpio_data = {
264 .gpio_base = OMAP_MAX_GPIO_LINES,
265 .irq_base = TWL4030_GPIO_IRQ_BASE,
266 .irq_end = TWL4030_GPIO_IRQ_END,
267 .pulldowns = BIT(2) | BIT(6) | BIT(8) | BIT(13)
268 | BIT(16) | BIT(17),
269 .setup = sdp3430_twl_gpio_setup,
270 };
271
272 /* regulator consumer mappings */
273
274 /* ads7846 on SPI */
275 static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = {
276 REGULATOR_SUPPLY("vcc", "spi1.0"),
277 };
278
279 static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = {
280 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
281 };
282
283 static struct regulator_consumer_supply sdp3430_vsim_supplies[] = {
284 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
285 };
286
287 static struct regulator_consumer_supply sdp3430_vmmc2_supplies[] = {
288 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
289 };
290
291 /*
292 * Apply all the fixed voltages since most versions of U-Boot
293 * don't bother with that initialization.
294 */
295
296 /* VAUX1 for mainboard (irda and sub-lcd) */
297 static struct regulator_init_data sdp3430_vaux1 = {
298 .constraints = {
299 .min_uV = 2800000,
300 .max_uV = 2800000,
301 .apply_uV = true,
302 .valid_modes_mask = REGULATOR_MODE_NORMAL
303 | REGULATOR_MODE_STANDBY,
304 .valid_ops_mask = REGULATOR_CHANGE_MODE
305 | REGULATOR_CHANGE_STATUS,
306 },
307 };
308
309 /* VAUX2 for camera module */
310 static struct regulator_init_data sdp3430_vaux2 = {
311 .constraints = {
312 .min_uV = 2800000,
313 .max_uV = 2800000,
314 .apply_uV = true,
315 .valid_modes_mask = REGULATOR_MODE_NORMAL
316 | REGULATOR_MODE_STANDBY,
317 .valid_ops_mask = REGULATOR_CHANGE_MODE
318 | REGULATOR_CHANGE_STATUS,
319 },
320 };
321
322 /* VAUX3 for LCD board */
323 static struct regulator_init_data sdp3430_vaux3 = {
324 .constraints = {
325 .min_uV = 2800000,
326 .max_uV = 2800000,
327 .apply_uV = true,
328 .valid_modes_mask = REGULATOR_MODE_NORMAL
329 | REGULATOR_MODE_STANDBY,
330 .valid_ops_mask = REGULATOR_CHANGE_MODE
331 | REGULATOR_CHANGE_STATUS,
332 },
333 .num_consumer_supplies = ARRAY_SIZE(sdp3430_vaux3_supplies),
334 .consumer_supplies = sdp3430_vaux3_supplies,
335 };
336
337 /* VAUX4 for OMAP VDD_CSI2 (camera) */
338 static struct regulator_init_data sdp3430_vaux4 = {
339 .constraints = {
340 .min_uV = 1800000,
341 .max_uV = 1800000,
342 .apply_uV = true,
343 .valid_modes_mask = REGULATOR_MODE_NORMAL
344 | REGULATOR_MODE_STANDBY,
345 .valid_ops_mask = REGULATOR_CHANGE_MODE
346 | REGULATOR_CHANGE_STATUS,
347 },
348 };
349
350 /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
351 static struct regulator_init_data sdp3430_vmmc1 = {
352 .constraints = {
353 .min_uV = 1850000,
354 .max_uV = 3150000,
355 .valid_modes_mask = REGULATOR_MODE_NORMAL
356 | REGULATOR_MODE_STANDBY,
357 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
358 | REGULATOR_CHANGE_MODE
359 | REGULATOR_CHANGE_STATUS,
360 },
361 .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc1_supplies),
362 .consumer_supplies = sdp3430_vmmc1_supplies,
363 };
364
365 /* VMMC2 for MMC2 card */
366 static struct regulator_init_data sdp3430_vmmc2 = {
367 .constraints = {
368 .min_uV = 1850000,
369 .max_uV = 1850000,
370 .apply_uV = true,
371 .valid_modes_mask = REGULATOR_MODE_NORMAL
372 | REGULATOR_MODE_STANDBY,
373 .valid_ops_mask = REGULATOR_CHANGE_MODE
374 | REGULATOR_CHANGE_STATUS,
375 },
376 .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc2_supplies),
377 .consumer_supplies = sdp3430_vmmc2_supplies,
378 };
379
380 /* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */
381 static struct regulator_init_data sdp3430_vsim = {
382 .constraints = {
383 .min_uV = 1800000,
384 .max_uV = 3000000,
385 .valid_modes_mask = REGULATOR_MODE_NORMAL
386 | REGULATOR_MODE_STANDBY,
387 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
388 | REGULATOR_CHANGE_MODE
389 | REGULATOR_CHANGE_STATUS,
390 },
391 .num_consumer_supplies = ARRAY_SIZE(sdp3430_vsim_supplies),
392 .consumer_supplies = sdp3430_vsim_supplies,
393 };
394
395 static struct twl4030_platform_data sdp3430_twldata = {
396 /* platform_data for children goes here */
397 .gpio = &sdp3430_gpio_data,
398 .keypad = &sdp3430_kp_data,
399
400 .vaux1 = &sdp3430_vaux1,
401 .vaux2 = &sdp3430_vaux2,
402 .vaux3 = &sdp3430_vaux3,
403 .vaux4 = &sdp3430_vaux4,
404 .vmmc1 = &sdp3430_vmmc1,
405 .vmmc2 = &sdp3430_vmmc2,
406 .vsim = &sdp3430_vsim,
407 };
408
omap3430_i2c_init(void)409 static int __init omap3430_i2c_init(void)
410 {
411 /* i2c1 for PMIC only */
412 omap3_pmic_get_config(&sdp3430_twldata,
413 TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_BCI |
414 TWL_COMMON_PDATA_MADC | TWL_COMMON_PDATA_AUDIO,
415 TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
416 sdp3430_twldata.vdac->constraints.apply_uV = true;
417 sdp3430_twldata.vpll2->constraints.apply_uV = true;
418 sdp3430_twldata.vpll2->constraints.name = "VDVI";
419
420 omap3_pmic_init("twl4030", &sdp3430_twldata);
421
422 /* i2c2 on camera connector (for sensor control) and optional isp1301 */
423 omap_register_i2c_bus(2, 400, NULL, 0);
424 /* i2c3 on display connector (for DVI, tfp410) */
425 omap_register_i2c_bus(3, 400, NULL, 0);
426 return 0;
427 }
428
429 #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
430
431 static struct omap_smc91x_platform_data board_smc91x_data = {
432 .cs = 3,
433 .flags = GPMC_MUX_ADD_DATA | GPMC_TIMINGS_SMC91C96 |
434 IORESOURCE_IRQ_LOWLEVEL,
435 };
436
board_smc91x_init(void)437 static void __init board_smc91x_init(void)
438 {
439 if (omap_rev() > OMAP3430_REV_ES1_0)
440 board_smc91x_data.gpio_irq = 6;
441 else
442 board_smc91x_data.gpio_irq = 29;
443
444 gpmc_smc91x_init(&board_smc91x_data);
445 }
446
447 #else
448
board_smc91x_init(void)449 static inline void board_smc91x_init(void)
450 {
451 }
452
453 #endif
454
enable_board_wakeup_source(void)455 static void enable_board_wakeup_source(void)
456 {
457 /* T2 interrupt line (keypad) */
458 omap_mux_init_signal("sys_nirq",
459 OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
460 }
461
462 static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
463
464 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
465 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
466 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
467
468 .phy_reset = true,
469 .reset_gpio_port[0] = 57,
470 .reset_gpio_port[1] = 61,
471 .reset_gpio_port[2] = -EINVAL
472 };
473
474 #ifdef CONFIG_OMAP_MUX
475 static struct omap_board_mux board_mux[] __initdata = {
476 { .reg_offset = OMAP_MUX_TERMINATOR },
477 };
478 #else
479 #define board_mux NULL
480 #endif
481
482 /*
483 * SDP3430 V2 Board CS organization
484 * Different from SDP3430 V1. Now 4 switches used to specify CS
485 *
486 * See also the Switch S8 settings in the comments.
487 */
488 static char chip_sel_3430[][GPMC_CS_NUM] = {
489 {PDC_NOR, PDC_NAND, PDC_ONENAND, DBG_MPDB, 0, 0, 0, 0}, /* S8:1111 */
490 {PDC_ONENAND, PDC_NAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1110 */
491 {PDC_NAND, PDC_ONENAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1101 */
492 };
493
494 static struct mtd_partition sdp_nor_partitions[] = {
495 /* bootloader (U-Boot, etc) in first sector */
496 {
497 .name = "Bootloader-NOR",
498 .offset = 0,
499 .size = SZ_256K,
500 .mask_flags = MTD_WRITEABLE, /* force read-only */
501 },
502 /* bootloader params in the next sector */
503 {
504 .name = "Params-NOR",
505 .offset = MTDPART_OFS_APPEND,
506 .size = SZ_256K,
507 .mask_flags = 0,
508 },
509 /* kernel */
510 {
511 .name = "Kernel-NOR",
512 .offset = MTDPART_OFS_APPEND,
513 .size = SZ_2M,
514 .mask_flags = 0
515 },
516 /* file system */
517 {
518 .name = "Filesystem-NOR",
519 .offset = MTDPART_OFS_APPEND,
520 .size = MTDPART_SIZ_FULL,
521 .mask_flags = 0
522 }
523 };
524
525 static struct mtd_partition sdp_onenand_partitions[] = {
526 {
527 .name = "X-Loader-OneNAND",
528 .offset = 0,
529 .size = 4 * (64 * 2048),
530 .mask_flags = MTD_WRITEABLE /* force read-only */
531 },
532 {
533 .name = "U-Boot-OneNAND",
534 .offset = MTDPART_OFS_APPEND,
535 .size = 2 * (64 * 2048),
536 .mask_flags = MTD_WRITEABLE /* force read-only */
537 },
538 {
539 .name = "U-Boot Environment-OneNAND",
540 .offset = MTDPART_OFS_APPEND,
541 .size = 1 * (64 * 2048),
542 },
543 {
544 .name = "Kernel-OneNAND",
545 .offset = MTDPART_OFS_APPEND,
546 .size = 16 * (64 * 2048),
547 },
548 {
549 .name = "File System-OneNAND",
550 .offset = MTDPART_OFS_APPEND,
551 .size = MTDPART_SIZ_FULL,
552 },
553 };
554
555 static struct mtd_partition sdp_nand_partitions[] = {
556 /* All the partition sizes are listed in terms of NAND block size */
557 {
558 .name = "X-Loader-NAND",
559 .offset = 0,
560 .size = 4 * (64 * 2048),
561 .mask_flags = MTD_WRITEABLE, /* force read-only */
562 },
563 {
564 .name = "U-Boot-NAND",
565 .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
566 .size = 10 * (64 * 2048),
567 .mask_flags = MTD_WRITEABLE, /* force read-only */
568 },
569 {
570 .name = "Boot Env-NAND",
571
572 .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */
573 .size = 6 * (64 * 2048),
574 },
575 {
576 .name = "Kernel-NAND",
577 .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
578 .size = 40 * (64 * 2048),
579 },
580 {
581 .name = "File System - NAND",
582 .size = MTDPART_SIZ_FULL,
583 .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */
584 },
585 };
586
587 static struct flash_partitions sdp_flash_partitions[] = {
588 {
589 .parts = sdp_nor_partitions,
590 .nr_parts = ARRAY_SIZE(sdp_nor_partitions),
591 },
592 {
593 .parts = sdp_onenand_partitions,
594 .nr_parts = ARRAY_SIZE(sdp_onenand_partitions),
595 },
596 {
597 .parts = sdp_nand_partitions,
598 .nr_parts = ARRAY_SIZE(sdp_nand_partitions),
599 },
600 };
601
omap_3430sdp_init(void)602 static void __init omap_3430sdp_init(void)
603 {
604 int gpio_pendown;
605
606 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
607 omap_board_config = sdp3430_config;
608 omap_board_config_size = ARRAY_SIZE(sdp3430_config);
609 omap3430_i2c_init();
610 omap_display_init(&sdp3430_dss_data);
611 if (omap_rev() > OMAP3430_REV_ES1_0)
612 gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV2;
613 else
614 gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV1;
615 omap_ads7846_init(1, gpio_pendown, 310, NULL);
616 omap_serial_init();
617 omap_sdrc_init(hyb18m512160af6_sdrc_params, NULL);
618 usb_musb_init(NULL);
619 board_smc91x_init();
620 board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
621 sdp3430_display_init();
622 enable_board_wakeup_source();
623 usbhs_init(&usbhs_bdata);
624 }
625
626 MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
627 /* Maintainer: Syed Khasim - Texas Instruments Inc */
628 .atag_offset = 0x100,
629 .reserve = omap_reserve,
630 .map_io = omap3_map_io,
631 .init_early = omap3430_init_early,
632 .init_irq = omap3_init_irq,
633 .handle_irq = omap3_intc_handle_irq,
634 .init_machine = omap_3430sdp_init,
635 .timer = &omap3_timer,
636 .restart = omap_prcm_restart,
637 MACHINE_END
638