Lines Matching +full:cs +full:- +full:gpio
4 * m5249sim.h -- ColdFire 5249 System Integration Module support.
51 #define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
52 #define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
53 #define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */
54 #define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
55 #define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
56 #define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
57 #define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
58 #define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
59 #define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
60 #define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
61 #define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
62 #define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
114 #define MCFSIM2_GPIOREAD (MCF_MBAR2 + 0x000) /* GPIO read values */
115 #define MCFSIM2_GPIOWRITE (MCF_MBAR2 + 0x004) /* GPIO write values */
116 #define MCFSIM2_GPIOENABLE (MCF_MBAR2 + 0x008) /* GPIO enabled */
117 #define MCFSIM2_GPIOFUNC (MCF_MBAR2 + 0x00C) /* GPIO function */
123 #define MCFSIM2_GPIOINTSTAT 0xc0 /* GPIO interrupt status */
124 #define MCFSIM2_GPIOINTCLEAR 0xc0 /* GPIO interrupt clear */
125 #define MCFSIM2_GPIOINTENABLE 0xc4 /* GPIO interrupt enable */
158 * Generic GPIO support
161 #define MCFGPIO_IRQ_MAX -1
162 #define MCFGPIO_IRQ_VECBASE -1
210 * PLL for 140MHz. Lets go fast :-)
247 orl %d0,0x4(%a1) /* de-assert IDE reset */