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/qemu/hw/ppc/
H A Dpegasos2.c652 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#size-cells", 0); in dt_usb()
653 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#address-cells", 1); in dt_usb()
660 uint32_t cells[3]; in dt_isa() local
662 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#size-cells", 1); in dt_isa()
663 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#address-cells", 2); in dt_isa()
671 cells[0] = cpu_to_be32(7); in dt_isa()
672 cells[1] = 0; in dt_isa()
674 cells, 2 * sizeof(cells[0])); in dt_isa()
675 cells[0] = cpu_to_be32(1); in dt_isa()
676 cells[1] = cpu_to_be32(0x3bc); in dt_isa()
[all …]
H A De500.c165 qemu_fdt_setprop_cells(fdt, node, "#gpio-cells", 2); in create_dt_mpc8xxx_gpio()
207 qemu_fdt_setprop_cell(fdt, i2c, "#size-cells", 0); in dt_i2c_create()
208 qemu_fdt_setprop_cell(fdt, i2c, "#address-cells", 1); in dt_i2c_create()
263 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1); in create_devtree_etsec()
264 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1); in create_devtree_etsec()
340 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1); in platform_bus_create_devtree()
341 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1); in platform_bus_create_devtree()
433 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2); in ppce500_load_device_tree()
434 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2); in ppce500_load_device_tree()
491 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1); in ppce500_load_device_tree()
[all …]
H A Dpnv_i2c.c453 _FDT((fdt_setprop_cell(fdt, i2c_bus_offset, "#address-cells", 1))); in pnv_i2c_bus_dt_xscom()
454 _FDT((fdt_setprop_cell(fdt, i2c_bus_offset, "#size-cells", 0))); in pnv_i2c_bus_dt_xscom()
489 _FDT((fdt_setprop_cell(fdt, i2c_offset, "#address-cells", 1))); in pnv_i2c_dt_xscom()
490 _FDT((fdt_setprop_cell(fdt, i2c_offset, "#size-cells", 0))); in pnv_i2c_dt_xscom()
H A Dpnv_lpc.c120 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2))); in pnv_lpc_dt_xscom()
121 _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1))); in pnv_lpc_dt_xscom()
169 _FDT((fdt_setprop_cell(fdt, lpcm_offset, "#address-cells", 1))); in pnv_dt_lpc()
170 _FDT((fdt_setprop_cell(fdt, lpcm_offset, "#size-cells", 1))); in pnv_dt_lpc()
222 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2))); in pnv_dt_lpc()
223 _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1))); in pnv_dt_lpc()
H A Dpnv_bmc.c97 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0x1))); in pnv_dt_bmc_sensors()
98 _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 0x0))); in pnv_dt_bmc_sensors()
/qemu/pc-bios/dtb/
H A Dcanyonlands.dts14 #address-cells = <2>;
15 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells = <0>;
57 #address-cells = <0>;
58 #size-cells = <0>;
59 #interrupt-cells = <2>;
67 #address-cells = <0>;
68 #size-cells = <0>;
69 #interrupt-cells = <2>;
[all …]
H A Dbamboo.dts15 #address-cells = <2>;
16 #size-cells = <1>;
27 #address-cells = <1>;
28 #size-cells = <0>;
55 #address-cells = <0x0>;
56 #size-cells = <0x0>;
57 #interrupt-cells = <0x2>;
72 #address-cells = <2>;
73 #size-cells = <1>;
89 #address-cells = <1>;
[all …]
H A Dpetalogix-ml605.dts11 #address-cells = < 0x01 >;
12 #size-cells = < 0x01 >;
32 #address-cells = < 0x01 >;
34 #size-cells = < 0x00 >;
135 #address-cells = < 0x01 >;
136 #size-cells = < 0x01 >;
169 #address-cells = < 0x01 >;
170 #size-cells = < 0x00 >;
235 #interrupt-cells = < 0x02 >;
244 #address-cells = < 0x01 >;
[all …]
H A Dpetalogix-s3adsp1800.dts11 #address-cells = <0x01>;
12 #size-cells = <0x01>;
27 #address-cells = <0x01>;
28 #size-cells = <0x00>;
112 #address-cells = <0x01>;
113 #size-cells = <0x01>;
259 #interrupt-cells = <0x02>;
/qemu/include/system/
H A Ddevice_tree.h142 * @values: array of number-of-cells, value pairs
145 * to be an array of cells. The values of the cells are specified via
146 * the values list, which alternates between "number of cells used by
148 * number-of-cells must be either 1 or 2 (other values will result in
150 * number of cells specified for it, an error is returned.
154 * the number of cells used for each element vary depending on the
155 * #address-cells and #size-cells properties of their parent node.
174 * @...: list of number-of-cells, value pairs
177 * to be an array of cells. The values of the cells are specified via
178 * the variable arguments, which alternates between "number of cells
/qemu/hw/riscv/
H A Dsifive_u.c102 uint32_t *cells; in create_fdt() local
123 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); in create_fdt()
124 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); in create_fdt()
129 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); in create_fdt()
130 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); in create_fdt()
140 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); in create_fdt()
151 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); in create_fdt()
166 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); in create_fdt()
167 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); in create_fdt()
193 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); in create_fdt()
[all …]
H A Dspike.c76 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); in create_fdt()
77 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); in create_fdt()
89 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); in create_fdt()
90 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); in create_fdt()
95 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); in create_fdt()
96 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); in create_fdt()
132 qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1); in create_fdt()
H A Dvirt.c202 /* Fill PCI address cells */ in create_pcie_irq_map()
206 /* Fill PCI Interrupt cells */ in create_pcie_irq_map()
210 /* Fill interrupt controller phandle and cells */ in create_pcie_irq_map()
295 qemu_fdt_setprop_cell(ms->fdt, intc_name, "#interrupt-cells", 1); in create_fdt_socket_cpus()
396 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); in create_fdt_socket_aclint()
437 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); in create_fdt_socket_aclint()
463 "#interrupt-cells", FDT_PLIC_INT_CELLS); in create_fdt_socket_plic()
465 "#address-cells", FDT_PLIC_ADDR_CELLS); in create_fdt_socket_plic()
568 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", in create_fdt_one_imsic()
646 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "#address-cells", in create_fdt_one_aplic()
[all …]
/qemu/hw/openrisc/
H A Dvirt.c143 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x1); in openrisc_create_fdt()
144 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x1); in openrisc_create_fdt()
149 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x1); in openrisc_create_fdt()
150 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x1); in openrisc_create_fdt()
161 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); in openrisc_create_fdt()
162 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); in openrisc_create_fdt()
180 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); in openrisc_create_fdt()
225 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 0); in openrisc_virt_ompic_init()
340 /* Fill PCI address cells */ in create_pcie_irq_map()
345 /* Fill PCI Interrupt cells */ in create_pcie_irq_map()
[all …]
H A Dopenrisc_sim.c125 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x1); in openrisc_create_fdt()
126 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x1); in openrisc_create_fdt()
137 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); in openrisc_create_fdt()
138 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); in openrisc_create_fdt()
156 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); in openrisc_create_fdt()
240 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 0); in openrisc_sim_ompic_init()
/qemu/ui/
H A Dconsole-vc.c59 TextCell *cells; member
210 c = &s->cells[y1 * s->width + x]; in console_show_cursor()
239 c = s->cells + y1 * s->width; in console_refresh()
362 ATTR2CHTYPE(s->cells[src].ch, in text_console_update()
363 s->cells[src].t_attrib.fgcol, in text_console_update()
364 s->cells[src].t_attrib.bgcol, in text_console_update()
365 s->cells[src].t_attrib.bold)); in text_console_update()
383 TextCell *cells, *c, *c1; in text_console_resize() local
400 cells = g_new(TextCell, t->width * t->total_height + 1); in text_console_resize()
402 c = &cells[y * t->width]; in text_console_resize()
[all …]
/qemu/hw/loongarch/
H A Dvirt-fdt-build.c34 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); in create_fdt()
35 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); in create_fdt()
54 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); in fdt_add_cpu_nodes()
55 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); in fdt_add_cpu_nodes()
229 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); in fdt_add_cpuic_node()
249 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); in fdt_add_eiointc_node()
276 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 2); in fdt_add_pch_pic_node()
338 /* Fill PCI address cells */ in fdt_add_pcie_irq_map_node()
342 /* Fill PCI Interrupt cells */ in fdt_add_pcie_irq_map_node()
346 /* Fill interrupt controller phandle and cells */ in fdt_add_pcie_irq_map_node()
[all …]
/qemu/hw/arm/
H A Draspi4b.c45 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells", in raspi_add_memory_node()
47 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells", in raspi_add_memory_node()
50 fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n"); in raspi_add_memory_node()
H A Dxlnx-versal-virt.c82 qemu_fdt_setprop_cell(s->fdt, "/", "#size-cells", 0x2); in fdt_create()
83 qemu_fdt_setprop_cell(s->fdt, "/", "#address-cells", 0x2); in fdt_create()
94 qemu_fdt_setprop_cell(s->fdt, name, "#clock-cells", 0x0); in fdt_add_clk_node()
104 qemu_fdt_setprop_cell(s->fdt, "/cpus", "#size-cells", 0x0); in fdt_add_cpu_nodes()
105 qemu_fdt_setprop_cell(s->fdt, "/cpus", "#address-cells", 1); in fdt_add_cpu_nodes()
140 qemu_fdt_setprop_cell(s->fdt, nodename, "#interrupt-cells", 3); in fdt_add_gic_nodes()
179 qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 2); in fdt_add_usb_xhci_nodes()
180 qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 2); in fdt_add_usb_xhci_nodes()
198 qemu_fdt_setprop_cells(s->fdt, name, "#stream-id-cells", 1); in fdt_add_usb_xhci_nodes()
318 qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 1); in fdt_add_gem_nodes()
[all …]
H A Dvirt.c284 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); in create_fdt()
285 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); in create_fdt()
322 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); in create_fdt()
432 * in the system, #address-cells can be set to 1, since in fdt_add_cpu_nodes()
438 * at least one of them has Aff3 populated, we set #address-cells to 2. in fdt_add_cpu_nodes()
450 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells); in fdt_add_cpu_nodes()
451 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); in fdt_add_cpu_nodes()
547 qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1); in fdt_add_its_gic_node()
585 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); in fdt_add_gic_node()
587 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); in fdt_add_gic_node()
[all …]
/qemu/hw/mips/
H A Dboston.c473 qemu_fdt_setprop_cell(fdt, name, "#address-cells", 3); in fdt_create_pcie()
474 qemu_fdt_setprop_cell(fdt, name, "#size-cells", 2); in fdt_create_pcie()
475 qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", 1); in fdt_create_pcie()
490 qemu_fdt_setprop_cell(fdt, intc_name, "#address-cells", 0); in fdt_create_pcie()
491 qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1); in fdt_create_pcie()
536 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x1); in create_fdt()
537 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x1); in create_fdt()
541 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); in create_fdt()
542 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); in create_fdt()
558 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x1); in create_fdt()
[all …]
/qemu/hw/i386/
H A Dmicrovm-dt.c116 qemu_fdt_setprop_cell(mms->fdt, nodename, "#address-cells", 3); in dt_add_pcie()
117 qemu_fdt_setprop_cell(mms->fdt, nodename, "#size-cells", 2); in dt_add_pcie()
175 qemu_fdt_setprop_cell(mms->fdt, nodename, "#interrupt-cells", 0x2); in dt_add_ioapic()
176 qemu_fdt_setprop_cell(mms->fdt, nodename, "#address-cells", 0x2); in dt_add_ioapic()
326 qemu_fdt_setprop_cell(mms->fdt, "/", "#address-cells", 0x2); in dt_setup_microvm()
327 qemu_fdt_setprop_cell(mms->fdt, "/", "#size-cells", 0x2); in dt_setup_microvm()
/qemu/pc-bios/
HDopenbios-sparc32( 8 H ! ` x p " p # $ 0 @ p % ` p x @ A B ( ...
/qemu/hw/misc/
H A Dmips_itu.c31 /* Initialize as 4kB area to fit all 32 cells with default 128B grain.
510 error_setg(errp, "Exceed maximum number of FIFO cells: %d", in mips_itu_realize()
515 error_setg(errp, "Exceed maximum number of Semaphore cells: %d", in mips_itu_realize()
/qemu/include/hw/misc/
H A Dmips_itu.h45 /* Circular buffer for FIFO. Semaphore cells use index 0 only */

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