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/qemu/target/openrisc/
H A Dsys_helper.c101 case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-127 */ in HELPER()
102 idx = spr - TO_SPR(1, 512); in HELPER()
104 if (mr & 1) { in HELPER()
107 if (rb & 1) { in HELPER()
112 case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-127 */ in HELPER()
113 idx = spr - TO_SPR(1, 640); in HELPER()
116 case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ in HELPER()
117 case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ in HELPER()
118 case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */ in HELPER()
119 case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */ in HELPER()
[all …]
/qemu/target/s390x/tcg/
H A Dvec_string_helper.c51 return (1 << es) * BITS_PER_BYTE; in get_element_bits()
59 return -1ull >> (64 - get_element_bits(es)); in get_single_element_mask()
67 return -1ull >> (65 - get_element_bits(es)); in get_single_element_lsbs_mask()
89 a1 = s390_vec_read_element64(v2, 1); in vfae()
91 b1 = s390_vec_read_element64(v3, 1); in vfae()
117 e0 = (e0 >> (bits - 1)) * get_single_element_mask(es); in vfae()
118 e1 = (e1 >> (bits - 1)) * get_single_element_mask(es); in vfae()
120 s390_vec_write_element64(v1, 1, e1); in vfae()
123 s390_vec_write_element64(v1, 1, 0); in vfae()
129 return 1; /* matching elements, no match for zero */ in vfae()
[all …]
/qemu/target/hexagon/imported/
H A Dldst.idef34 …=memub","Load Unsigned Byte",ATTRIBS(A_MEMSIZE_1B,A_LOAD,A_REGWRSIZE_1B),"0",fLOAD(1,1,u,EA,RdV),0)
35 STD_LD_AMODES(loadrb, "Rd32=memb", "Load signed Byte",ATTRIBS(A_MEMSIZE_1B,A_LOAD),"0",fLOAD(1,1,s,…
36 …"Load unsigned Half integer",ATTRIBS(A_REGWRSIZE_2B,A_MEMSIZE_2B,A_LOAD),"1",fLOAD(1,2,u,EA,RdV),1)
37 …, "Load signed Half integer",ATTRIBS(A_REGWRSIZE_2B,A_MEMSIZE_2B,A_LOAD),"1",fLOAD(1,2,s,EA,RdV),1)
38 …ri, "Rd32=memw", "Load Word",ATTRIBS(A_REGWRSIZE_4B,A_MEMSIZE_4B,A_LOAD),"2",fLOAD(1,4,u,EA,RdV),2)
39 …memd","Load Double integer",ATTRIBS(A_REGWRSIZE_8B,A_MEMSIZE_8B,A_LOAD),"3",fLOAD(1,8,u,EA,RddV),3)
43 ATTRIBS(A_LOAD),"1",
45 fLOAD(1,2,u,EA,tmpV);
49 },1)
54 fLOAD(1,4,u,EA,tmpV);
[all …]
/qemu/hw/ide/
H A Dsii3112.c65 val = d->i.bmdma[1].cmd; in sii3112_reg_read()
68 val = d->regs[1].swdata; in sii3112_reg_read()
71 val = d->i.bmdma[1].status; in sii3112_reg_read()
77 val = bmdma_addr_ioport_ops.read(&d->i.bmdma[1], addr - 12, size); in sii3112_reg_read()
81 val |= (d->regs[0].confstat & (1UL << 11) ? (1 << 4) : 0); /*SATAINT0*/ in sii3112_reg_read()
82 val |= (d->regs[1].confstat & (1UL << 11) ? (1 << 6) : 0); /*SATAINT1*/ in sii3112_reg_read()
83 val |= (d->i.bmdma[1].status & BM_STATUS_INT ? (1 << 14) : 0); in sii3112_reg_read()
85 val |= (uint32_t)d->i.bmdma[1].status << 24; in sii3112_reg_read()
88 val = d->i.bmdma[1].cmd; in sii3112_reg_read()
89 val |= (d->regs[1].confstat & (1UL << 11) ? (1 << 4) : 0); in sii3112_reg_read()
[all …]
/qemu/tests/qtest/
H A Dtest-arm-mptimer.c14 #define TIMER_BLOCK_SCALE(s) ((((s) & 0xff) + 1) * 10)
17 clock_step(TIMER_BLOCK_SCALE(scaler) * (int64_t)(steps_nb) + 1)
26 #define TIMER_CONTROL_ENABLE (1 << 0)
27 #define TIMER_CONTROL_PERIODIC (1 << 1)
28 #define TIMER_CONTROL_IT_ENABLE (1 << 2)
31 #define PERIODIC 1
61 writel(TIMER_BASE_PHYS + TIMER_INTSTAT, 1); in timer_int_clr()
108 g_assert_cmpuint(timer_get_and_clr_int_sts(), ==, 1); in test_timer_oneshot()
148 g_assert_cmpuint(timer_get_and_clr_int_sts(), ==, 1); in test_timer_pause()
188 clock_step(TIMER_BLOCK_SCALE(scaler) * (101 + repeat) + 1); in test_timer_periodic()
[all …]
/qemu/tests/tcg/xtensa/
H A Dtest_lsc.S9 movi a2, 1
12 movi a2, 1f
21 movi a3, 1f + 8
34 1:
35 .float 1, 2, 3
40 movi a2, 1f
55 movi a3, 1f + 8
68 1:
74 movi a2, 1f
86 movi a3, 1f + 8
[all …]
/qemu/hw/pci-host/
H A Dmv64361.c90 memory_region_init(&s->mem, OBJECT(dev), name, 1ULL << 32); in mv64361_pcihost_realize()
155 MV64361_IRQ_DEVERR = 1,
243 for (mask = 1, i = 0; i < 21; i++, mask <<= 1) { in set_mem_windows()
257 p->remap[4], (p->io_size + 1) << 16, in set_mem_windows()
266 p->remap[0], (p->mem_size[0] + 1) << 16, in set_mem_windows()
275 p->remap[1], (p->mem_size[1] + 1) << 16, in set_mem_windows()
276 (p->mem_base[1] & 0xfffff) << 16); in set_mem_windows()
284 p->remap[2], (p->mem_size[2] + 1) << 16, in set_mem_windows()
293 p->remap[3], (p->mem_size[3] + 1) << 16, in set_mem_windows()
297 p = &s->pci[1]; in set_mem_windows()
[all …]
/qemu/include/hw/char/
H A Davr_usart.h38 #define USART_CSRA_RXC (1 << 7)
39 #define USART_CSRA_TXC (1 << 6)
40 #define USART_CSRA_DRE (1 << 5)
41 #define USART_CSRA_MPCM (1 << 0)
43 #define USART_CSRB_RXCIE (1 << 7)
44 #define USART_CSRB_TXCIE (1 << 6)
45 #define USART_CSRB_DREIE (1 << 5)
46 #define USART_CSRB_RXEN (1 << 4)
47 #define USART_CSRB_TXEN (1 << 3)
48 #define USART_CSRB_CSZ2 (1 << 2)
[all …]
/qemu/include/hw/net/
H A Dallwinner_emac.h95 #define EMAC_CTL_RESET (1 << 0)
96 #define EMAC_CTL_TX_EN (1 << 1)
97 #define EMAC_CTL_RX_EN (1 << 2)
100 #define EMAC_TX_MODE_ABORTED_FRAME_EN (1 << 0)
101 #define EMAC_TX_MODE_DMA_EN (1 << 1)
104 #define EMAC_RX_CTL_AUTO_DRQ_EN (1 << 1)
105 #define EMAC_RX_CTL_DMA_EN (1 << 2)
106 #define EMAC_RX_CTL_PASS_ALL_EN (1 << 4)
107 #define EMAC_RX_CTL_PASS_CTL_EN (1 << 5)
108 #define EMAC_RX_CTL_PASS_CRC_ERR_EN (1 << 6)
[all …]
/qemu/target/alpha/
H A Dcpu.h34 ALPHA_EV3 = 1,
46 ALPHA_EV4_3 = 1,
51 ALPHA_LCA_1 = 1, /* 21066 */
61 ALPHA_EV5_1 = 1, /* Rev BA, CA */
70 ALPHA_EV45_1 = 1, /* Pass 1 */
77 ALPHA_EV56_1 = 1, /* Pass 1 */
83 IMPLVER_21164 = 1, /* EV5, EV56 & PCA45 */
129 #define FPCR_SUM (1U << (63 - 32))
130 #define FPCR_INED (1U << (62 - 32))
131 #define FPCR_UNFD (1U << (61 - 32))
[all …]
/qemu/include/hw/timer/
H A Dimx_gpt.h48 #define GPT_CR_EN (1 << 0) /* GPT Enable */
49 #define GPT_CR_ENMOD (1 << 1) /* GPT Enable Mode */
50 #define GPT_CR_DBGEN (1 << 2) /* GPT Debug mode enable */
51 #define GPT_CR_WAITEN (1 << 3) /* GPT Wait Mode Enable */
52 #define GPT_CR_DOZEN (1 << 4) /* GPT Doze mode enable */
53 #define GPT_CR_STOPEN (1 << 5) /* GPT Stop Mode Enable */
57 #define GPT_CR_FRR (1 << 9) /* Freerun or Restart */
58 #define GPT_CR_SWR (1 << 15) /* Software Reset */
59 #define GPT_CR_IM1 (3 << 16) /* Input capture channel 1 mode (2 bits) */
61 #define GPT_CR_OM1 (7 << 20) /* Output Compare Channel 1 Mode (3 bits) */
[all …]
/qemu/pc-bios/s390-ccw/
H A Dcio.h21 u32 qf:1; /* qdio facility */
22 u32 w:1;
25 u32 ena:1; /* enabled */
28 u32 mp:1; /* multipath mode */
29 u32 tf:1; /* timing facility */
30 u32 dnv:1; /* device number valid */
43 u32 mbfc:1; /* measurement block format control */
44 u32 xmwme:1; /* extended measurement word mode enable */
45 u32 csense:1; /* concurrent sense; can be enabled ...*/
57 u32 ena:1;
[all …]
/qemu/tests/functional/
H A Dtest_mem_addr_space.py19 # the VM generates empty logs. A delay of 1 second is added for
21 DELAY_Q35_BOOT_SEQUENCE = 1
35 # bits == 1 -> 32-bit; bits == 2 -> 64-bit
36 bits = int.from_bytes(fh.read(1), byteorder='little')
50 hotpluggable memory size is 60 GiB. Per slot, we reserve 1 GiB of memory
62 self.vm.add_args('-S', '-m', '512,slots=1,maxmem=59.6G',
64 '-object', 'memory-backend-ram,id=mem1,size=1G',
69 self.assertEqual(self.vm.exitcode(), 1, "QEMU exit code should be 1")
80 self.vm.add_args('-S', '-m', '512,slots=1,maxmem=59.6G',
82 '-object', 'memory-backend-ram,id=mem1,size=1G',
[all …]
/qemu/tests/tcg/arm/system/
H A Dtest-armv6m-undef.S17 * terminate with exit code 0 on success or 1 on failure.
42 .word exc_reset_thumb /* 1. Reset */
58 .equ exc_reset_thumb, exc_reset + 1
93 b 1f
95 1:
98 b 1f
100 1:
102 bl 1f
103 1:
104 b 1f
[all …]
/qemu/tests/qemu-iotests/
H A D08533 status=1 # failure is the default!
44 for i in $(seq 1 ${SNAPSHOTS})
49 for img in "${TEST_IMG}".{1,2,base}
55 trap "_cleanup; exit \$status" 0 1 2 3 15
66 # ${1}: unique identifier for the snapshot filename
71 'snapshot-file':'${TEST_DIR}/${1}-${snapshot_virt0}',
76 # ${1}: unique identifier for the snapshot filename
83 'snapshot-file': '${TEST_DIR}/${1}-${snapshot_virt0}' } },
86 'snapshot-file': '${TEST_DIR}/${1}-${snapshot_virt1}' } } ]
92 # ${1}: unique identifier for the snapshot filename
[all …]
H A D24428 status=1 # failure is the default!
36 trap "_cleanup; exit \$status" 0 1 2 3 15
58 $QEMU_IO -c "open $TEST_IMG" -c "read -P 0 0 64k" 2>&1 | _filter_qemu_io | _filter_testdir
59 $QEMU_IO -c "open -odata-file.filename=$TEST_IMG.data $TEST_IMG" -c "read -P 0 0 64k" 2>&1 | _filte…
60 $QEMU_IO -c "open -odata-file.filename=inexistent $TEST_IMG" -c "read -P 0 0 64k" 2>&1 | _filter_qe…
66 $QEMU_IO -c "open $TEST_IMG" -c "read -P 0 0 64k" 2>&1 | _filter_qemu_io | _filter_testdir
67 $QEMU_IO -c "open -odata-file.filename=$TEST_IMG.data $TEST_IMG" -c "read -P 0 0 64k" 2>&1 | _filte…
68 $QEMU_IO -c "open -odata-file.filename=inexistent $TEST_IMG" -c "read -P 0 0 64k" 2>&1 | _filter_qe…
74 $QEMU_IO -c "open -odata-file.filename=$TEST_IMG.data $TEST_IMG" -c "read -P 0 0 64k" 2>&1 | _filte…
75 $QEMU_IO -c "open -odata-file.filename=inexistent $TEST_IMG" -c "read -P 0 0 64k" 2>&1 | _filter_qe…
[all …]
/qemu/target/arm/tcg/
H A Dt32.decode56 # rdahi: bits [3:1] from insn, bit 0 is 1
57 # rdalo: bits [3:1] from insn, bit 0 is 0
65 @s_rrr_shi ....... .... s:1 rn:4 .... rd:4 .. shty:2 rm:4 \
67 @s_rxr_shi ....... .... s:1 .... .... rd:4 .. shty:2 rm:4 \
70 &s_rrr_shi shim=%imm5_12_6 s=1 rd=0
81 TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
86 # The v8.1M MVE shift insns overlap in encoding with MOVS/ORRS
90 # (eg "using a new shift insn on a v8.1M CPU without MVE"), and letting
95 UQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 00 1111 @mve_sh_ri
96 LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
[all …]
H A Dneon-ls.decode31 %vd_dp 22:1 12:4
35 VLDST_multiple 1111 0100 0 . l:1 0 rn:4 .... itype:4 size:2 align:2 rm:4 \
40 VLD_all_lanes 1111 0100 1 . 1 0 rn:4 .... 11 n:2 size:2 t:1 a:1 rm:4 \
44 %imm1_5_p1 5:1 !function=plus_1
45 %imm1_6_p1 6:1 !function=plus_1
47 VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 00 n:2 reg_idx:3 align:1 rm:4 \
48 vd=%vd_dp size=0 stride=1
49 VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 01 n:2 reg_idx:2 . align:1 rm:4 \
50 vd=%vd_dp size=1 stride=%imm1_5_p1
51 VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 10 n:2 reg_idx:1 . align:2 rm:4 \
/qemu/tcg/loongarch64/
H A Dtcg-target-has.h13 #define TCG_TARGET_HAS_extr_i64_i32 1
23 #define TCG_TARGET_HAS_not_vec 1
24 #define TCG_TARGET_HAS_neg_vec 1
26 #define TCG_TARGET_HAS_andc_vec 1
27 #define TCG_TARGET_HAS_orc_vec 1
29 #define TCG_TARGET_HAS_nor_vec 1
31 #define TCG_TARGET_HAS_mul_vec 1
32 #define TCG_TARGET_HAS_shi_vec 1
34 #define TCG_TARGET_HAS_shv_vec 1
35 #define TCG_TARGET_HAS_roti_vec 1
[all …]
/qemu/scripts/oss-fuzz/
H A Dminimize_qtest_trace.py23 write_suffix_lookup = {"b": (1, "B"),
57 rc = subprocess.Popen("timeout -s 9 {timeout}s {qemu_path} {qemu_args} 2>&1\
95 if i <=(HINT_LEN-1):
100 l = i-1
105 k += 1
106 l -= 1
108 l -= 1
115 for j in range(1, HINT_LEN):
119 step = int(writes[0].split()[1], 16) - int(writes[1].split()[1], 16)
120 for j in range(1, HINT_LEN-1):
[all …]
/qemu/hw/char/
H A Drenesas_sci.c36 FIELD(SMR, MP, 2, 1)
37 FIELD(SMR, STOP, 3, 1)
38 FIELD(SMR, PM, 4, 1)
39 FIELD(SMR, PE, 5, 1)
40 FIELD(SMR, CHR, 6, 1)
41 FIELD(SMR, CM, 7, 1)
42 REG8(BRR, 1)
45 FIELD(SCR, TEIE, 2, 1)
46 FIELD(SCR, MPIE, 3, 1)
47 FIELD(SCR, RE, 4, 1)
[all …]
/qemu/tests/tcg/alpha/
H A Dtest-cvttq.c3 #define FPCR_SUM (1UL << 63)
4 #define FPCR_INED (1UL << 62)
5 #define FPCR_UNFD (1UL << 61)
6 #define FPCR_UNDZ (1UL << 60)
9 #define FPCR_DYN_MINUS (1UL << FPCR_DYN_SHIFT)
13 #define FPCR_IOV (1UL << 57)
14 #define FPCR_INE (1UL << 56)
15 #define FPCR_UNF (1UL << 55)
16 #define FPCR_OVF (1UL << 54)
17 #define FPCR_DZE (1UL << 53)
[all …]
/qemu/include/standard-headers/asm-x86/
H A Dbootparam.h13 #define LOADED_HIGH (1<<0)
14 #define KASLR_FLAG (1<<1)
15 #define QUIET_FLAG (1<<5)
16 #define KEEP_SEGMENTS (1<<6)
17 #define CAN_USE_HEAP (1<<7)
20 #define XLF_KERNEL_64 (1<<0)
21 #define XLF_CAN_BE_LOADED_ABOVE_4G (1<<1)
22 #define XLF_EFI_HANDOVER_32 (1<<2)
23 #define XLF_EFI_HANDOVER_64 (1<<3)
24 #define XLF_EFI_KEXEC (1<<4)
[all …]
/qemu/include/qemu/
H A Dcpuid.h19 /* Leaf 1, %edx */
21 #define bit_CMOV (1 << 15)
24 #define bit_SSE2 (1 << 26)
27 /* Leaf 1, %ecx */
29 #define bit_PCLMUL (1 << 1)
32 #define bit_SSE4_1 (1 << 19)
35 #define bit_MOVBE (1 << 22)
38 #define bit_OSXSAVE (1 << 27)
41 #define bit_AVX (1 << 28)
46 #define bit_BMI (1 << 3)
[all …]
/qemu/include/hw/i386/
H A Dapic_internal.h32 #define APIC_LVT_THERMAL 1
41 #define APIC_DM_LOWPRI 1
50 #define APIC_DESTMODE_LOGICAL 1
55 #define APIC_TRIGGER_LEVEL 1
69 #define APIC_LVT_TIMER_PERIODIC (1 << APIC_LVT_TIMER_SHIFT)
70 #define APIC_LVT_MASKED (1 << APIC_LVT_MASKED_SHIFT)
71 #define APIC_LVT_LEVEL_TRIGGER (1 << APIC_LVT_LEVEL_TRIGGER_SHIFT)
72 #define APIC_LVT_REMOTE_IRR (1 << APIC_LVT_REMOTE_IRR_SHIFT)
73 #define APIC_LVT_INT_POLARITY (1 << APIC_LVT_INT_POLARITY_SHIFT)
74 #define APIC_LVT_DELIV_STS (1 << APIC_LVT_DELIV_STS_SHIFT)
[all …]

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