Lines Matching full:1
90 memory_region_init(&s->mem, OBJECT(dev), name, 1ULL << 32); in mv64361_pcihost_realize()
155 MV64361_IRQ_DEVERR = 1,
243 for (mask = 1, i = 0; i < 21; i++, mask <<= 1) { in set_mem_windows()
257 p->remap[4], (p->io_size + 1) << 16, in set_mem_windows()
266 p->remap[0], (p->mem_size[0] + 1) << 16, in set_mem_windows()
275 p->remap[1], (p->mem_size[1] + 1) << 16, in set_mem_windows()
276 (p->mem_base[1] & 0xfffff) << 16); in set_mem_windows()
284 p->remap[2], (p->mem_size[2] + 1) << 16, in set_mem_windows()
293 p->remap[3], (p->mem_size[3] + 1) << 16, in set_mem_windows()
297 p = &s->pci[1]; in set_mem_windows()
302 p->remap[4], (p->io_size + 1) << 16, in set_mem_windows()
306 p = &s->pci[1]; in set_mem_windows()
311 p->remap[0], (p->mem_size[0] + 1) << 16, in set_mem_windows()
315 p = &s->pci[1]; in set_mem_windows()
320 p->remap[1], (p->mem_size[1] + 1) << 16, in set_mem_windows()
321 (p->mem_base[1] & 0xfffff) << 16); in set_mem_windows()
324 p = &s->pci[1]; in set_mem_windows()
329 p->remap[2], (p->mem_size[2] + 1) << 16, in set_mem_windows()
333 p = &s->pci[1]; in set_mem_windows()
338 p->remap[3], (p->mem_size[3] + 1) << 16, in set_mem_windows()
402 ret = s->pci[0].mem_base[1]; in mv64361_read()
405 ret = s->pci[0].mem_size[1]; in mv64361_read()
408 ret = (s->pci[0].remap[1] & 0xffff0000) >> 16; in mv64361_read()
411 ret = s->pci[0].remap[1] >> 32; in mv64361_read()
438 ret = s->pci[1].io_base; in mv64361_read()
441 ret = s->pci[1].io_size; in mv64361_read()
444 ret = s->pci[1].remap[4] >> 16; in mv64361_read()
447 ret = s->pci[1].mem_base[0]; in mv64361_read()
450 ret = s->pci[1].mem_size[0]; in mv64361_read()
453 ret = (s->pci[1].remap[0] & 0xffff0000) >> 16; in mv64361_read()
456 ret = s->pci[1].remap[0] >> 32; in mv64361_read()
459 ret = s->pci[1].mem_base[1]; in mv64361_read()
462 ret = s->pci[1].mem_size[1]; in mv64361_read()
465 ret = (s->pci[1].remap[1] & 0xffff0000) >> 16; in mv64361_read()
468 ret = s->pci[1].remap[1] >> 32; in mv64361_read()
471 ret = s->pci[1].mem_base[2]; in mv64361_read()
474 ret = s->pci[1].mem_size[2]; in mv64361_read()
477 ret = (s->pci[1].remap[2] & 0xffff0000) >> 16; in mv64361_read()
480 ret = s->pci[1].remap[2] >> 32; in mv64361_read()
483 ret = s->pci[1].mem_base[3]; in mv64361_read()
486 ret = s->pci[1].mem_size[3]; in mv64361_read()
489 ret = (s->pci[1].remap[3] & 0xffff0000) >> 16; in mv64361_read()
492 ret = s->pci[1].remap[3] >> 32; in mv64361_read()
509 ret = pci_host_conf_le_ops.read(PCI_HOST_BRIDGE(&s->pci[1]), 0, size); in mv64361_read()
513 ret = pci_host_data_le_ops.read(PCI_HOST_BRIDGE(&s->pci[1]), in mv64361_read()
586 if ((val & 0x3000000ULL) >> 24 != 1) { in warn_swap_bit()
642 s->pci[0].mem_base[1] = val & 0x70fffffULL; in mv64361_write()
645 mv64361_set_pci_mem_remap(s, 0, 1, val, false); in mv64361_write()
649 s->pci[0].mem_size[1] = val & 0xffffULL; in mv64361_write()
653 mv64361_set_pci_mem_remap(s, 0, 1, val, in mv64361_write()
687 s->pci[1].io_base = val & 0x30fffffULL; in mv64361_write()
690 s->pci[1].remap[4] = (val & 0xffffULL) << 16; in mv64361_write()
694 s->pci[1].io_size = val & 0xffffULL; in mv64361_write()
697 s->pci[1].mem_base[0] = val & 0x70fffffULL; in mv64361_write()
700 mv64361_set_pci_mem_remap(s, 1, 0, val, false); in mv64361_write()
704 s->pci[1].mem_size[0] = val & 0xffffULL; in mv64361_write()
708 mv64361_set_pci_mem_remap(s, 1, 0, val, in mv64361_write()
712 s->pci[1].mem_base[1] = val & 0x70fffffULL; in mv64361_write()
715 mv64361_set_pci_mem_remap(s, 1, 1, val, false); in mv64361_write()
719 s->pci[1].mem_size[1] = val & 0xffffULL; in mv64361_write()
723 mv64361_set_pci_mem_remap(s, 1, 1, val, in mv64361_write()
727 s->pci[1].mem_base[2] = val & 0x70fffffULL; in mv64361_write()
730 mv64361_set_pci_mem_remap(s, 1, 2, val, false); in mv64361_write()
734 s->pci[1].mem_size[2] = val & 0xffffULL; in mv64361_write()
738 mv64361_set_pci_mem_remap(s, 1, 2, val, in mv64361_write()
742 s->pci[1].mem_base[3] = val & 0x70fffffULL; in mv64361_write()
745 mv64361_set_pci_mem_remap(s, 1, 3, val, false); in mv64361_write()
749 s->pci[1].mem_size[3] = val & 0xffffULL; in mv64361_write()
753 mv64361_set_pci_mem_remap(s, 1, 3, val, in mv64361_write()
771 pci_host_conf_le_ops.write(PCI_HOST_BRIDGE(&s->pci[1]), 0, val, size); in mv64361_write()
775 pci_host_data_le_ops.write(PCI_HOST_BRIDGE(&s->pci[1]), in mv64361_write()
833 .valid.min_access_size = 1,
852 mv64361_update_irq(opaque, MV64361_IRQ_P0_GPP0_7 + n / 8, 1); in mv64361_gpp_irq()
900 s->pci[0].mem_base[1] = 0x100f900; in mv64361_reset()
901 s->pci[0].mem_size[1] = 0xff; in mv64361_reset()
906 s->pci[1].io_base = 0x100fe00; in mv64361_reset()
907 s->pci[1].io_size = 0xff; in mv64361_reset()
908 s->pci[1].mem_base[0] = 0x1008000; in mv64361_reset()
909 s->pci[1].mem_size[0] = 0x3fff; in mv64361_reset()
910 s->pci[1].mem_base[1] = 0x100fd00; in mv64361_reset()
911 s->pci[1].mem_size[1] = 0xff; in mv64361_reset()
912 s->pci[1].mem_base[2] = 0x1002600; in mv64361_reset()
913 s->pci[1].mem_size[2] = 0x1ff; in mv64361_reset()
914 s->pci[1].mem_base[3] = 0x100ff80; in mv64361_reset()
915 s->pci[1].mem_size[3] = 0x7f; in mv64361_reset()
921 s->pci[0].remap[1] = 0; in mv64361_reset()
922 s->pci[1].remap[1] = 0; in mv64361_reset()