65         val = d->i.bmdma[1].cmd;  in sii3112_reg_read()
68         val = d->regs[1].swdata;  in sii3112_reg_read()
71         val = d->i.bmdma[1].status;  in sii3112_reg_read()
77         val = bmdma_addr_ioport_ops.read(&d->i.bmdma[1], addr - 12, size);  in sii3112_reg_read()
81         val |= (d->regs[0].confstat & (1UL << 11) ? (1 << 4) : 0); /*SATAINT0*/  in sii3112_reg_read()
82         val |= (d->regs[1].confstat & (1UL << 11) ? (1 << 6) : 0); /*SATAINT1*/  in sii3112_reg_read()
83         val |= (d->i.bmdma[1].status & BM_STATUS_INT ? (1 << 14) : 0);  in sii3112_reg_read()
85         val |= (uint32_t)d->i.bmdma[1].status << 24;  in sii3112_reg_read()
88         val = d->i.bmdma[1].cmd;  in sii3112_reg_read()
89         val |= (d->regs[1].confstat & (1UL << 11) ? (1 << 4) : 0);  in sii3112_reg_read()
90         val |= (uint32_t)d->i.bmdma[1].status << 16;  in sii3112_reg_read()
102         val = pci_ide_data_le_ops.read(&d->i.bus[1], addr - 0xc0, size);  in sii3112_reg_read()
105         val = pci_ide_cmd_le_ops.read(&d->i.bus[1], 2, size);  in sii3112_reg_read()
108         val = d->regs[1].confstat;  in sii3112_reg_read()
120         val = d->regs[1].scontrol;  in sii3112_reg_read()
123         val = (d->i.bus[1].ifs[0].blk) ? 0x113 : 0;  in sii3112_reg_read()
126         val = (uint32_t)d->regs[1].sien << 16;  in sii3112_reg_read()
160         bmdma_cmd_writeb(&d->i.bmdma[1], val);  in sii3112_reg_write()
164         d->regs[1].swdata = val & 0x3f;  in sii3112_reg_write()
168         bmdma_status_writeb(&d->i.bmdma[1], val);  in sii3112_reg_write()
171         bmdma_addr_ioport_ops.write(&d->i.bmdma[1], addr - 12, val, size);  in sii3112_reg_write()
180         pci_ide_data_le_ops.write(&d->i.bus[1], addr - 0xc0, val, size);  in sii3112_reg_write()
183         pci_ide_cmd_le_ops.write(&d->i.bus[1], 2, val, size);  in sii3112_reg_write()
187         if (val & 1) {  in sii3112_reg_write()
195         d->regs[1].scontrol = val & 0xfff;  in sii3112_reg_write()
196         if (val & 1) {  in sii3112_reg_write()
197             ide_bus_reset(&d->i.bus[1]);  in sii3112_reg_write()
201         d->regs[1].sien = (val >> 16) & 0x3eed;  in sii3112_reg_write()
220         set |= s->regs[i].confstat & (1UL << 11);  in sii3112_update_irq()
222     pci_set_irq(PCI_DEVICE(s), (set ? 1 : 0));  in sii3112_update_irq()
231         s->regs[channel].confstat |= (1UL << 11);  in sii3112_set_irq()
233         s->regs[channel].confstat &= ~(1UL << 11);  in sii3112_set_irq()
258     pci_config_set_interrupt_pin(dev->config, 1);  in sii3112_pci_realize()
267     mr = g_new(MemoryRegion, 1);  in sii3112_pci_realize()
270     mr = g_new(MemoryRegion, 1);  in sii3112_pci_realize()
272     pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, mr);  in sii3112_pci_realize()
273     mr = g_new(MemoryRegion, 1);  in sii3112_pci_realize()
276     mr = g_new(MemoryRegion, 1);  in sii3112_pci_realize()
279     mr = g_new(MemoryRegion, 1);  in sii3112_pci_realize()
285         ide_bus_init(&s->bus[i], sizeof(s->bus[i]), ds, i, 1);  in sii3112_pci_realize()
301     pd->revision = 1;  in sii3112_pci_class_init()