Lines Matching full:1
34 ALPHA_EV3 = 1,
46 ALPHA_EV4_3 = 1,
51 ALPHA_LCA_1 = 1, /* 21066 */
61 ALPHA_EV5_1 = 1, /* Rev BA, CA */
70 ALPHA_EV45_1 = 1, /* Pass 1 */
77 ALPHA_EV56_1 = 1, /* Pass 1 */
83 IMPLVER_21164 = 1, /* EV5, EV56 & PCA45 */
129 #define FPCR_SUM (1U << (63 - 32))
130 #define FPCR_INED (1U << (62 - 32))
131 #define FPCR_UNFD (1U << (61 - 32))
132 #define FPCR_UNDZ (1U << (60 - 32))
135 #define FPCR_DYN_MINUS (1U << FPCR_DYN_SHIFT)
139 #define FPCR_IOV (1U << (57 - 32))
140 #define FPCR_INE (1U << (56 - 32))
141 #define FPCR_UNF (1U << (55 - 32))
142 #define FPCR_OVF (1U << (54 - 32))
143 #define FPCR_DZE (1U << (53 - 32))
144 #define FPCR_INV (1U << (52 - 32))
145 #define FPCR_OVFD (1U << (51 - 32))
146 #define FPCR_DZED (1U << (50 - 32))
147 #define FPCR_INVD (1U << (49 - 32))
148 #define FPCR_DNZ (1U << (48 - 32))
149 #define FPCR_DNOD (1U << (47 - 32))
157 #define SWCR_TRAP_ENABLE_INV (1U << 1)
158 #define SWCR_TRAP_ENABLE_DZE (1U << 2)
159 #define SWCR_TRAP_ENABLE_OVF (1U << 3)
160 #define SWCR_TRAP_ENABLE_UNF (1U << 4)
161 #define SWCR_TRAP_ENABLE_INE (1U << 5)
162 #define SWCR_TRAP_ENABLE_DNO (1U << 6)
163 #define SWCR_TRAP_ENABLE_MASK ((1U << 7) - (1U << 1))
165 #define SWCR_MAP_DMZ (1U << 12)
166 #define SWCR_MAP_UMZ (1U << 13)
169 #define SWCR_STATUS_INV (1U << 17)
170 #define SWCR_STATUS_DZE (1U << 18)
171 #define SWCR_STATUS_OVF (1U << 19)
172 #define SWCR_STATUS_UNF (1U << 20)
173 #define SWCR_STATUS_INE (1U << 21)
174 #define SWCR_STATUS_DNO (1U << 22)
175 #define SWCR_STATUS_MASK ((1U << 23) - (1U << 17))
197 #define MMU_USER_IDX 1
318 /* OSF/1 Page table bits. */
351 EXC_M_SWC = 1, /* Software completion */
377 #define ENV_FLAG_PAL_MODE (1u << ENV_FLAG_PAL_SHIFT)
379 #define ENV_FLAG_RX_FLAG (1u << ENV_FLAG_RX_SHIFT)
380 #define ENV_FLAG_FEN (1u << ENV_FLAG_FEN_SHIFT)
385 #define TB_FLAG_UNALIGN (1u << 1)
398 IR_T0 = 1,