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/qemu/target/arm/tcg/
H A Diwmmxt_helper.c32 #define SIMD8_SET(v, n, b) ((v != 0) << ((((b) + 1) * 4) + (n)))
33 #define SIMD16_SET(v, n, h) ((v != 0) << ((((h) + 1) * 8) + (n)))
34 #define SIMD32_SET(v, n, w) ((v != 0) << ((((w) + 1) * 16) + (n)))
35 #define SIMD64_SET(v, n) ((v != 0) << (32 + (n)))
42 #define NBIT8(x) ((x) & 0x80)
43 #define NBIT16(x) ((x) & 0x8000)
44 #define NBIT32(x) ((x) & 0x80000000)
45 #define NBIT64(x) ((x) & 0x8000000000000000ULL)
46 #define ZBIT8(x) (((x) & 0xff) == 0)
47 #define ZBIT16(x) (((x) & 0xffff) == 0)
[all …]
/qemu/disas/
H A Dm68k.c35 fields is contiguous. We number the bits with 0 being the most significant
67 /* Sign bit is always one bit long. 1 means negative, 0 means positive. */
74 very large number (e.g., given the exp_bias of 0x3fff and a 64
143 /* Opcode table header for m680[01234]0/m6888[12]/m68851.
165 #define _m68k_undef 0
166 #define m68000 0x001
168 #define m68010 0x002
169 #define m68020 0x004
170 #define m68030 0x008
173 #define m68040 0x010
[all …]
/qemu/target/i386/tcg/
H A Dint_helper.c37 num = (env->regs[R_EAX] & 0xffff); in helper_divb_AL()
38 den = (t0 & 0xff); in helper_divb_AL()
39 if (den == 0) { in helper_divb_AL()
43 if (q > 0xff) { in helper_divb_AL()
46 q &= 0xff; in helper_divb_AL()
47 r = (num % den) & 0xff; in helper_divb_AL()
48 env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | (r << 8) | q; in helper_divb_AL()
57 if (den == 0) { in helper_idivb_AL()
64 q &= 0xff; in helper_idivb_AL()
65 r = (num % den) & 0xff; in helper_idivb_AL()
[all …]
H A Dseg_helper.c36 if ((sp_mask) == 0xffff) { \
37 env->regs[R_ESP] = (env->regs[R_ESP] & ~0xffff) | \
38 ((val) & 0xffff); \
39 } else if ((sp_mask) == 0xffffffffLL) { \
44 } while (0)
50 } while (0)
99 if (!(env->cr[0] & CR0_PG_MASK)) { in get_pg_mode()
100 return 0; in get_pg_mode()
102 if (env->cr[0] & CR0_WP_MASK) { in get_pg_mode()
134 int mmu_index_32 = (env->hflags & HF_LMA_MASK) ? 0 : 1; in x86_mmu_index_kernel_pl()
[all …]
/qemu/bsd-user/i386/
H A Dtarget_arch_reg.h57 regs->r_fs = env->segs[R_FS].selector & 0xffff; in target_copy_regs()
58 regs->r_es = env->segs[R_ES].selector & 0xffff; in target_copy_regs()
59 regs->r_ds = env->segs[R_DS].selector & 0xffff; in target_copy_regs()
73 regs->r_cs = env->segs[R_CS].selector & 0xffff; in target_copy_regs()
78 regs->r_ss = env->segs[R_SS].selector & 0xffff; in target_copy_regs()
79 regs->r_gs = env->segs[R_GS].selector & 0xffff; in target_copy_regs()
/qemu/bsd-user/x86_64/
H A Dtarget_arch_reg.h80 regs->r_fs = env->segs[R_FS].selector & 0xffff; in target_copy_regs()
81 regs->r_gs = env->segs[R_GS].selector & 0xffff; in target_copy_regs()
83 regs->r_es = env->segs[R_ES].selector & 0xffff; in target_copy_regs()
84 regs->r_ds = env->segs[R_DS].selector & 0xffff; in target_copy_regs()
86 regs->r_cs = env->segs[R_CS].selector & 0xffff; in target_copy_regs()
89 regs->r_ss = env->segs[R_SS].selector & 0xffff; in target_copy_regs()
/qemu/tests/unit/
H A Dtest-resv-mem.c16 #define DEBUG 0
22 int i = 0; in print_ranges()
31 printf("%s rev[%i] = [0x%"PRIx64",0x%"PRIx64"]\n", in print_ranges()
95 in = insert_sorted_range(in, 0x10000, UINT64_MAX); in check_range_reverse_array()
96 expected = insert_sorted_range(expected, 0x0, 0xFFFF); in check_range_reverse_array()
97 run_range_inverse_array("test1", &in, &expected, 0x0, UINT64_MAX); in check_range_reverse_array()
101 in = insert_sorted_range(in, 0x10000, 0xFFFFFFFFFFFF); in check_range_reverse_array()
102 expected = insert_sorted_range(expected, 0x0, 0xFFFF); in check_range_reverse_array()
103 expected = insert_sorted_range(expected, 0x1000000000000, UINT64_MAX); in check_range_reverse_array()
104 run_range_inverse_array("test1", &in, &expected, 0x0, UINT64_MAX); in check_range_reverse_array()
[all …]
/qemu/tests/tcg/ppc64/
H A Dvector.c8 vector unsigned char vbc_bi_src = { 0xFF, 0xFF, 0, 0xFF, 0xFF, 0xFF, in main()
9 0xFF, 0xFF, 0xFF, 0xFF, 0, 0, 0, in main()
10 0, 0xFF, 0xFF}; in main()
11 vector unsigned short vbc_hi_src = { 0xFFFF, 0, 0, 0xFFFF, in main()
12 0, 0, 0xFFFF, 0xFFFF}; in main()
13 vector unsigned int vbc_wi_src = {0, 0, 0xFFFFFFFF, 0xFFFFFFFF}; in main()
14 vector unsigned long long vbc_di_src = {0xFFFFFFFFFFFFFFFF, 0}; in main()
17 asm("vextractbm %0, %1" : "=r" (result_wi) : "v" (vbc_bi_src)); in main()
19 assert(result_wi == 0b1101111111000011); in main()
21 assert(result_wi == 0b1100001111111011); in main()
[all …]
/qemu/tests/tcg/openrisc/
H A Dtest_addi.c8 b = 0x01; in main()
9 result = 0x00; in main()
11 ("l.addi %0, %1, 0xffff\n\t" in main()
20 b = 0x010000; in main()
21 result = 0xffff; in main()
23 ("l.addi %0, %1, 0xffff\n\t" in main()
32 return 0; in main()
/qemu/hw/net/
H A Digb.c84 #define IGB_CAP_SRIOV_OFFSET (0x160)
85 #define IGB_VF_OFFSET (0x80)
88 #define E1000E_MMIO_IDX 0
138 if (s->ioaddr < 0x1FFFF) { in igb_io_get_reg_index()
143 if (s->ioaddr < 0x7FFFF) { in igb_io_get_reg_index()
148 if (s->ioaddr < 0xFFFFF) { in igb_io_get_reg_index()
161 uint32_t idx = 0; in igb_io_read()
174 return 0; in igb_io_read()
177 return 0; in igb_io_read()
185 uint32_t idx = 0; in igb_io_write()
[all …]
H A De1000e.c87 #define E1000E_MMIO_IDX 0
97 #define E1000E_MSIX_TABLE (0x0000)
98 #define E1000E_MSIX_PBA (0x2000)
118 if (s->ioaddr < 0x1FFFF) { in e1000e_io_get_reg_index()
123 if (s->ioaddr < 0x7FFFF) { in e1000e_io_get_reg_index()
128 if (s->ioaddr < 0xFFFFF) { in e1000e_io_get_reg_index()
141 uint32_t idx = 0; in e1000e_io_read()
154 return 0; in e1000e_io_read()
157 return 0; in e1000e_io_read()
166 uint32_t idx = 0; in e1000e_io_write()
[all …]
H A De1000.c62 } while (0)
64 #define DBGOUT(what, fmt, ...) do {} while (0)
67 #define IOPORT_SIZE 0x40
68 #define PNPMMIO_SIZE 0x20000
90 uint32_t mac_reg[0x8000];
91 uint16_t phy_reg[0x20];
101 unsigned char data[0x10000];
129 /* Compatibility flags for migration to/from qemu 1.3.0 and older */
183 /* bits 0-5 reserved; MII_BMCR_[ANRESTART,RESET] are self clearing */ in set_phy_ctrl()
184 s->phy_reg[MII_BMCR] = val & ~(0x3f | in set_phy_ctrl()
[all …]
H A Dlance.c27 * AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000
61 trace_lance_mem_writew(addr, val & 0xffff); in lance_mem_write()
62 pcnet_ioport_writew(&d->state, addr, val & 0xffff); in lance_mem_write()
72 trace_lance_mem_readw(addr, val & 0xffff); in lance_mem_read()
73 return val & 0xffff; in lance_mem_read()
98 VMSTATE_STRUCT(state, SysBusPCNetState, 0, vmstate_pcnet, PCNetState),
136 "bootindex", "/ethernet-phy@0", in lance_instance_init()
H A Dtulip.c75 if (s->csr[0] & CSR0_DBO) { in tulip_desc_read()
93 if (s->csr[0] & CSR0_DBO) { in tulip_desc_write()
138 desc->control & 0x7ff, (desc->control >> 11) & 0x7ff, in tulip_dump_tx_descriptor()
147 desc->control & 0x7ff, (desc->control >> 11) & 0x7ff, in tulip_dump_rx_descriptor()
160 (((s->csr[0] >> CSR0_DSL_SHIFT) & CSR0_DSL_MASK) << 2); in tulip_next_rx_descriptor()
198 static const char broadcast[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; in tulip_filter_address()
202 for (i = 0; i < 16 && ret == false; i++) { in tulip_filter_address()
218 if ((s->csr[6] & CSR6_PM) && (addr[0] & 1)) { in tulip_filter_address()
238 return 0; in tulip_receive()
254 desc.status = 0; in tulip_receive()
[all …]
/qemu/include/hw/usb/
H A Ddwc2-regs.h47 #define GOTGCTL HSOTG_REG(0x000)
49 #define GOTGCTL_MULT_VALID_BC_MASK (0x1f << 22)
62 #define GOTGCTL_SESREQSCS BIT(0)
64 #define GOTGINT HSOTG_REG(0x004)
72 #define GAHBCFG HSOTG_REG(0x008)
79 #define GAHBCFG_HBSTLEN_MASK (0xf << 1)
81 #define GAHBCFG_HBSTLEN_SINGLE 0
86 #define GAHBCFG_GLBL_INTR_EN BIT(0)
92 #define GUSBCFG HSOTG_REG(0x00C)
109 #define GUSBCFG_USBTRDTIM_MASK (0xf << 10)
[all …]
/qemu/hw/misc/
H A Dstm32f2xx_syscfg.c31 #define STM_SYSCFG_ERR_DEBUG 0
38 } while (0)
46 s->syscfg_memrmp = 0x00000000; in stm32f2xx_syscfg_reset()
47 s->syscfg_pmc = 0x00000000; in stm32f2xx_syscfg_reset()
48 s->syscfg_exticr1 = 0x00000000; in stm32f2xx_syscfg_reset()
49 s->syscfg_exticr2 = 0x00000000; in stm32f2xx_syscfg_reset()
50 s->syscfg_exticr3 = 0x00000000; in stm32f2xx_syscfg_reset()
51 s->syscfg_exticr4 = 0x00000000; in stm32f2xx_syscfg_reset()
52 s->syscfg_cmpcr = 0x00000000; in stm32f2xx_syscfg_reset()
60 DB_PRINT("0x%"HWADDR_PRIx"\n", addr); in stm32f2xx_syscfg_read()
[all …]
/qemu/target/arm/
H A Dsyndrome.h32 EC_UNCATEGORIZED = 0x00,
33 EC_WFX_TRAP = 0x01,
34 EC_CP15RTTRAP = 0x03,
35 EC_CP15RRTTRAP = 0x04,
36 EC_CP14RTTRAP = 0x05,
37 EC_CP14DTTRAP = 0x06,
38 EC_ADVSIMDFPACCESSTRAP = 0x07,
39 EC_FPIDTRAP = 0x08,
40 EC_PACTRAP = 0x09,
41 EC_BXJTRAP = 0x0a,
[all …]
/qemu/hw/char/
H A Dimx_serial.c33 #define DEBUG_IMX_UART 0
42 } while (0)
80 usr1 |= (s->ucr2 & UCR2_ATEN) ? (s->usr1 & USR1_AGTIM) : 0; in imx_update()
85 mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0; in imx_update()
89 * RDR and DREN are both bit 0 in imx_update()
116 return 0; in imx_serial_rx_fifo_pop()
158 s->ucr1 = 0; in imx_serial_reset()
160 s->ucr3 = 0x700; in imx_serial_reset()
161 s->ubmr = 0; in imx_serial_reset()
163 s->ufcr = BIT(11) | BIT(0); in imx_serial_reset()
[all …]
/qemu/hw/pci/
H A Dpci_bridge.c56 if (pos < 0) { in pci_bridge_ssvid_init()
135 limit |= 0xfff; /* PCI bridge spec 3.2.5.6. */ in pci_bridge_get_limit()
143 limit |= 0xfffff; /* PCI bridge spec 3.2.5.{1, 8}. */ in pci_bridge_get_limit()
157 /* TODO: this doesn't handle base = 0 limit = 2^64 - 1 correctly. in pci_bridge_init_alias()
159 pcibus_t size = enabled && limit >= base ? limit + 1 - base : 0; in pci_bridge_init_alias()
277 /* Trigger hot reset on 0->1 transition. */ in pci_bridge_write_config()
287 PCI_IO_RANGE_MASK & 0xff); in pci_bridge_disable_base_limit()
289 PCI_IO_RANGE_MASK & 0xff); in pci_bridge_disable_base_limit()
291 PCI_MEMORY_RANGE_MASK & 0xffff); in pci_bridge_disable_base_limit()
293 PCI_MEMORY_RANGE_MASK & 0xffff); in pci_bridge_disable_base_limit()
[all …]
/qemu/hw/timer/
H A Dcmsdk-apb-dualtimer.c32 REG32(TIMER1LOAD, 0x0)
33 REG32(TIMER1VALUE, 0x4)
34 REG32(TIMER1CONTROL, 0x8)
35 FIELD(CONTROL, ONESHOT, 0, 1)
44 REG32(TIMER1INTCLR, 0xc)
45 REG32(TIMER1RIS, 0x10)
46 REG32(TIMER1MIS, 0x14)
47 REG32(TIMER1BGLOAD, 0x18)
48 REG32(TIMER2LOAD, 0x20)
49 REG32(TIMER2VALUE, 0x24)
[all …]
/qemu/target/tricore/
H A Dop_helper.c58 (in case of PSW.IS = 0). The stack pointer bit is set for using the in raise_exception_sync_internal()
60 if ((env->PSW & MASK_PSW_IS) == 0) { in raise_exception_sync_internal()
68 /*The current Protection Register Set is set to 0: PSW.PRS = 00 B .*/ in raise_exception_sync_internal()
78 /* Write permission to global registers A[0], A[1], A[8], A[9] is in raise_exception_sync_internal()
79 disabled: PSW.GW = 0. */ in raise_exception_sync_internal()
82 /*The interrupt system is globally disabled: ICR.IE = 0. The ‘old’ in raise_exception_sync_internal()
99 raise_exception_sync_internal(env, class, tin, 0, 0); in helper_raise_exception_sync()
105 raise_exception_sync_internal(env, class, tin, pc, 0); in raise_exception_sync_helper()
113 uint8_t low = (uint8_t)(val & 0xff); in reverse16()
117 rl = (uint16_t)((high * 0x0202020202ULL & 0x010884422010ULL) % 1023); in reverse16()
[all …]
/qemu/linux-headers/asm-arm/
H A Dkvm.h38 #define KVM_ARM_SVC_sp svc_regs[0]
41 #define KVM_ARM_ABT_sp abt_regs[0]
44 #define KVM_ARM_UND_sp und_regs[0]
47 #define KVM_ARM_IRQ_sp irq_regs[0]
52 #define KVM_ARM_FIQ_r8 fiq_regs[0]
71 #define KVM_ARM_TARGET_CORTEX_A15 0
76 #define KVM_ARM_DEVICE_TYPE_SHIFT 0
77 #define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
79 #define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT)
82 #define KVM_ARM_DEVICE_VGIC_V2 0
[all …]
/qemu/hw/i386/
H A Dvmmouse.c40 #define VMMOUSE_READ_ID 0x45414552
41 #define VMMOUSE_DISABLE 0x000000f5
42 #define VMMOUSE_REQUEST_RELATIVE 0x4c455252
43 #define VMMOUSE_REQUEST_ABSOLUTE 0x53424152
47 #define VMMOUSE_VERSION 0x3442554a
49 #define VMMOUSE_RELATIVE_PACKET 0x00010000
51 #define VMMOUSE_LEFT_BUTTON 0x20
52 #define VMMOUSE_RIGHT_BUTTON 0x10
53 #define VMMOUSE_MIDDLE_BUTTON 0x08
55 #define VMMOUSE_MIN_X 0
[all …]
/qemu/hw/dma/
H A Domap_dma.c127 #define TIMEOUT_INTR (1 << 0)
154 a->src = ch->addr[0]; in omap_dma_channel_load()
159 a->frame = 0; in omap_dma_channel_load()
160 a->element = 0; in omap_dma_channel_load()
161 a->pck_element = 0; in omap_dma_channel_load()
168 for (i = 0; i < 2; i ++) in omap_dma_channel_load()
171 a->elem_delta[i] = 0; in omap_dma_channel_load()
172 a->frame_delta[i] = 0; in omap_dma_channel_load()
176 a->frame_delta[i] = 0; in omap_dma_channel_load()
180 ch->element_index[omap_3_1 ? 0 : i] - 1; in omap_dma_channel_load()
[all …]
/qemu/tests/tcg/x86_64/system/
H A Dboot.S47 ELFNOTE(Xen, XEN_ELFNOTE_VIRT_BASE, _ASM_PTR 0x100000)
50 ELFNOTE(Xen, XEN_ELFNOTE_PADDR_OFFSET, _ASM_PTR 0)
59 * - `cr0`: bit 0 (PE) must be set. All the other writable bits are cleared.
61 * - `cs `: must be a 32-bit read/execute code segment with a base of ‘0’
62 * and a limit of ‘0xFFFFFFFF’. The selector value is unspecified.
64 * ‘0’ and a limit of ‘0xFFFFFFFF’. The selector values are all
66 * - `tr`: must be a 32-bit TSS (active) with a base of '0' and a limit
67 * of '0x67'.
82 ljmp $0x8,$.Lloadcs
84 mov $0x10,%eax
[all …]

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