33 #define DEBUG_IMX_UART 0
42     } while (0)
80     usr1 |= (s->ucr2 & UCR2_ATEN) ? (s->usr1 & USR1_AGTIM) : 0;  in imx_update()
85     mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;  in imx_update()
89      * RDR and DREN are both bit 0  in imx_update()
116         return 0;  in imx_serial_rx_fifo_pop()
158     s->ucr1 = 0;  in imx_serial_reset()
160     s->ucr3 = 0x700;  in imx_serial_reset()
161     s->ubmr = 0;  in imx_serial_reset()
163     s->ufcr = BIT(11) | BIT(0);  in imx_serial_reset()
195     case 0x0: /* URXD */  in imx_serial_read()
205             if (rx_used == 0) {  in imx_serial_read()
216     case 0x20: /* UCR1 */  in imx_serial_read()
220     case 0x21: /* UCR2 */  in imx_serial_read()
224     case 0x25: /* USR1 */  in imx_serial_read()
228     case 0x26: /* USR2 */  in imx_serial_read()
232     case 0x2A: /* BRM Modulator */  in imx_serial_read()
236     case 0x2B: /* Baud Rate Count */  in imx_serial_read()
240     case 0x2d: /* Test register */  in imx_serial_read()
244     case 0x24: /* UFCR */  in imx_serial_read()
248     case 0x2c:  in imx_serial_read()
252     case 0x22: /* UCR3 */  in imx_serial_read()
256     case 0x23: /* UCR4 */  in imx_serial_read()
260     case 0x29: /* BRM Incremental */  in imx_serial_read()
261         value = 0x0; /* TODO */  in imx_serial_read()
265         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"  in imx_serial_read()
267         value = 0;  in imx_serial_read()
286     case 0x10: /* UTXD */  in imx_serial_write()
301     case 0x20: /* UCR1 */  in imx_serial_write()
302         s->ucr1 = value & 0xffff;  in imx_serial_write()
309     case 0x21: /* UCR2 */  in imx_serial_write()
325         s->ucr2 = value & 0xffff;  in imx_serial_write()
328     case 0x25: /* USR1 */  in imx_serial_write()
334     case 0x26: /* USR2 */  in imx_serial_write()
349     case 0x29: /* UBIR */  in imx_serial_write()
350         s->ubrc = value & 0xffff;  in imx_serial_write()
353     case 0x2a: /* UBMR */  in imx_serial_write()
354         s->ubmr = value & 0xffff;  in imx_serial_write()
357     case 0x2c: /* One ms reg */  in imx_serial_write()
358         s->onems = value & 0xffff;  in imx_serial_write()
361     case 0x24: /* FIFO control register */  in imx_serial_write()
362         s->ufcr = value & 0xffff;  in imx_serial_write()
365     case 0x22: /* UCR3 */  in imx_serial_write()
366         s->ucr3 = value & 0xffff;  in imx_serial_write()
369     case 0x23: /* UCR4 */  in imx_serial_write()
370         s->ucr4 = value & 0xffff;  in imx_serial_write()
374     case 0x2d: /* UTS1 */  in imx_serial_write()
375         qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"  in imx_serial_write()
381         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"  in imx_serial_write()
390     return s->ucr2 & UCR2_RXEN ? fifo32_num_free(&s->rx_fifo) : 0;  in imx_can_receive()
422     for (int i = 0; i < size; i++) {  in imx_receive()
461                           TYPE_IMX_SERIAL, 0x1000);  in imx_serial_init()