32 REG32(TIMER1LOAD, 0x0)
33 REG32(TIMER1VALUE, 0x4)
34 REG32(TIMER1CONTROL, 0x8)
35     FIELD(CONTROL, ONESHOT, 0, 1)
44 REG32(TIMER1INTCLR, 0xc)
45 REG32(TIMER1RIS, 0x10)
46 REG32(TIMER1MIS, 0x14)
47 REG32(TIMER1BGLOAD, 0x18)
48 REG32(TIMER2LOAD, 0x20)
49 REG32(TIMER2VALUE, 0x24)
50 REG32(TIMER2CONTROL, 0x28)
51 REG32(TIMER2INTCLR, 0x2c)
52 REG32(TIMER2RIS, 0x30)
53 REG32(TIMER2MIS, 0x34)
54 REG32(TIMER2BGLOAD, 0x38)
55 REG32(TIMERITCR, 0xf00)
56     FIELD(TIMERITCR, ENABLE, 0, 1)
58 REG32(TIMERITOP, 0xf04)
59     FIELD(TIMERITOP, TIMINT1, 0, 1)
63 REG32(PID4, 0xfd0)
64 REG32(PID5, 0xfd4)
65 REG32(PID6, 0xfd8)
66 REG32(PID7, 0xfdc)
67 REG32(PID0, 0xfe0)
68 REG32(PID1, 0xfe4)
69 REG32(PID2, 0xfe8)
70 REG32(PID3, 0xfec)
71 REG32(CID0, 0xff0)
72 REG32(CID1, 0xff4)
73 REG32(CID2, 0xff8)
74 REG32(CID3, 0xffc)
78     0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
79     0x23, 0xb8, 0x1b, 0x00, /* PID0..PID3 */
80     0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
98         timint1 = cmsdk_dualtimermod_intstatus(&s->timermod[0]);  in cmsdk_apb_dualtimer_update()
104     qemu_set_irq(s->timermod[0].timerint, timint1);  in cmsdk_apb_dualtimer_update()
113     case 0:  in cmsdk_dualtimermod_divisor()
146         case 0:  in cmsdk_dualtimermod_write_control()
158                           "CMSDK APB dual-timer: CONTROL.PRESCALE==0b11"  in cmsdk_dualtimermod_write_control()
177                 load = deposit32(m->load, 0, 16, load);  in cmsdk_dualtimermod_write_control()
180             load = 0xffffffff;  in cmsdk_dualtimermod_write_control()
183             load &= 0xffff;  in cmsdk_dualtimermod_write_control()
185         ptimer_set_limit(m->timer, load, 0);  in cmsdk_dualtimermod_write_control()
196             value = deposit32(m->value, 0, 16, value);  in cmsdk_dualtimermod_write_control()
200             value &= 0xffff;  in cmsdk_dualtimermod_write_control()
206                 load = deposit32(m->load, 0, 16, load);  in cmsdk_dualtimermod_write_control()
209                 load &= 0xffff;  in cmsdk_dualtimermod_write_control()
214                 load = 0xffffffff;  in cmsdk_dualtimermod_write_control()
216                 load = 0xffff;  in cmsdk_dualtimermod_write_control()
220         ptimer_set_limit(m->timer, load, 0);  in cmsdk_dualtimermod_write_control()
257             r = 0;  in cmsdk_apb_dualtimer_read()
270         switch (offset & 0x1F) {  in cmsdk_apb_dualtimer_read()
280                     r = deposit32(m->load, 0, 16, r);  in cmsdk_apb_dualtimer_read()
290                 r = deposit32(m->value, 0, 16, r);  in cmsdk_apb_dualtimer_read()
345         switch (offset & 0x1F) {  in cmsdk_apb_dualtimer_write()
351                 value &= 0xffff;  in cmsdk_apb_dualtimer_write()
380                 value &= 0xffff;  in cmsdk_apb_dualtimer_write()
383             ptimer_set_limit(m->timer, value, 0);  in cmsdk_apb_dualtimer_write()
391             m->intstatus = 0;  in cmsdk_apb_dualtimer_write()
422     m->intstatus = 0;  in cmsdk_dualtimermod_reset()
423     m->load = 0;  in cmsdk_dualtimermod_reset()
424     m->value = 0xffffffff;  in cmsdk_dualtimermod_reset()
428      * We start in free-running mode, with VALUE at 0xffffffff, and  in cmsdk_dualtimermod_reset()
430      * limit must both be set to 0xffff, so we wrap at 16 bits.  in cmsdk_dualtimermod_reset()
432     ptimer_set_limit(m->timer, 0xffff, 1);  in cmsdk_dualtimermod_reset()
445     for (i = 0; i < ARRAY_SIZE(s->timermod); i++) {  in cmsdk_apb_dualtimer_reset()
448     s->timeritcr = 0;  in cmsdk_apb_dualtimer_reset()
449     s->timeritop = 0;  in cmsdk_apb_dualtimer_reset()
457     for (i = 0; i < ARRAY_SIZE(s->timermod); i++) {  in cmsdk_apb_dualtimer_clk_update()
473                           s, "cmsdk-apb-dualtimer", 0x1000);  in cmsdk_apb_dualtimer_init()
477     for (i = 0; i < ARRAY_SIZE(s->timermod); i++) {  in cmsdk_apb_dualtimer_init()
495     for (i = 0; i < ARRAY_SIZE(s->timermod); i++) {  in cmsdk_apb_dualtimer_realize()