Lines Matching +full:0 +full:xffff
62 } while (0)
64 #define DBGOUT(what, fmt, ...) do {} while (0)
67 #define IOPORT_SIZE 0x40
68 #define PNPMMIO_SIZE 0x20000
90 uint32_t mac_reg[0x8000];
91 uint16_t phy_reg[0x20];
101 unsigned char data[0x10000];
129 /* Compatibility flags for migration to/from qemu 1.3.0 and older */
183 /* bits 0-5 reserved; MII_BMCR_[ANRESTART,RESET] are self clearing */ in set_phy_ctrl()
184 s->phy_reg[MII_BMCR] = val & ~(0x3f | in set_phy_ctrl()
205 static const char phy_regcap[0x20] = {
232 [MII_PHYID1] = 0x141,
244 [M88E1000_PHY_SPEC_CTRL] = 0x360,
245 [M88E1000_PHY_SPEC_STATUS] = 0xac00,
246 [M88E1000_EXT_PHY_SPEC_CTRL] = 0x0d60,
250 [PBA] = 0x00100030,
251 [LEDCTL] = 0x602,
254 [STATUS] = 0x80000000 | E1000_STATUS_GIO_MASTER_ENABLE |
263 /* Helper function, *curr == 0 means the value is not set */
267 if (value && (*curr == 0 || value < *curr)) { in mit_update_delay()
308 * RDTR!=0), TADV and ITR. in set_interrupt_cause()
311 mit_delay = 0; in set_interrupt_cause()
332 s->mit_ide = 0; in set_interrupt_cause()
335 s->mit_irq_level = (pending_ints != 0); in set_interrupt_cause()
344 s->mit_timer_on = 0; in e1000_mit_timer()
346 set_interrupt_cause(s, 0, s->mac_reg[ICR]); in e1000_mit_timer()
354 set_interrupt_cause(s, 0, val | s->mac_reg[ICR]); in set_ics()
363 set_ics(s, 0, E1000_ICS_LSC); /* signal link status change to guest */ in e1000_autoneg_timer()
383 d->mit_timer_on = 0; in e1000_reset_hold()
384 d->mit_irq_level = 0; in e1000_reset_hold()
385 d->mit_ide = 0; in e1000_reset_hold()
386 memset(d->phy_reg, 0, sizeof d->phy_reg); in e1000_reset_hold()
389 memset(d->mac_reg, 0, sizeof d->mac_reg); in e1000_reset_hold()
392 memset(&d->tx, 0, sizeof d->tx); in e1000_reset_hold()
426 DBGOUT(RX, "RCTL: %d, mac_reg[RCTL] = 0x%x\n", s->mac_reg[RDT], in set_rx_control()
441 DBGOUT(MDIC, "MDIC read reg 0x%x\n", addr); in set_mdic()
448 DBGOUT(MDIC, "MDIC write reg 0x%x, value 0x%x\n", addr, data); in set_mdic()
463 set_ics(s, 0, E1000_ICR_MDAC); in set_mdic()
475 ((s->eeprom_data[(s->eecd_state.bitnum_out >> 4) & 0x3f] >> in get_eecd()
476 ((s->eecd_state.bitnum_out & 0xf) ^ 0xf))) & 1) in get_eecd()
492 s->eecd_state.val_in = 0; in set_eecd()
493 s->eecd_state.bitnum_in = 0; in set_eecd()
494 s->eecd_state.bitnum_out = 0; in set_eecd()
495 s->eecd_state.reading = 0; in set_eecd()
508 s->eecd_state.bitnum_out = ((s->eecd_state.val_in & 0x3f)<<4)-1; in set_eecd()
522 if ((s->mac_reg[EERD] & E1000_EEPROM_RW_REG_START) == 0) in flash_eerd_read()
610 phsum = (phsum >> 16) + (phsum & 0xffff); in xmit_seg()
643 unsigned int split_size = txd_lower & 0xffff, bytes, sz; in process_tx_desc()
644 unsigned int msh = 0xfffff; in process_tx_desc()
654 tp->tso_frames = 0; in process_tx_desc()
657 s->use_tso_for_migration = 0; in process_tx_desc()
662 if (tp->size == 0) { in process_tx_desc()
665 tp->cptse = (txd_lower & E1000_TXD_CMD_TSE) ? 1 : 0; in process_tx_desc()
668 tp->cptse = 0; in process_tx_desc()
720 tp->tso_frames = 0; in process_tx_desc()
721 tp->sum_needed = 0; in process_tx_desc()
722 tp->vlan_needed = 0; in process_tx_desc()
723 tp->size = 0; in process_tx_desc()
724 tp->cptse = 0; in process_tx_desc()
734 return 0; in txdesc_writeback()
746 uint64_t bal = s->mac_reg[TDBAL] & ~0xf; in tx_desc_base()
782 s->mac_reg[TDH] = 0; in start_xmit()
796 set_ics(s, 0, cause); in start_xmit()
825 set_ics(s, 0, E1000_ICR_LSC); in e1000_set_link_status()
858 uint64_t bal = s->mac_reg[RDBAL] & ~0xf; in rx_desc_base()
869 set_ics(s, 0, E1000_ICS_RXO); in e1000_receiver_overrun()
881 uint16_t vlan_special = 0; in e1000_receive_iov()
882 uint8_t vlan_status = 0; in e1000_receive_iov()
886 size_t iov_ofs = 0; in e1000_receive_iov()
897 return 0; in e1000_receive_iov()
902 iov_to_buf(iov, iovcnt, 0, min_buf, MAXIMUM_ETHERNET_HDR_LEN); in e1000_receive_iov()
934 desc_offset = 0; in e1000_receive_iov()
965 iov_ofs = 0; in e1000_receive_iov()
987 s->mac_reg[RDH] = 0; in e1000_receive_iov()
1007 set_ics(s, 0, n); in e1000_receive_iov()
1035 set_interrupt_cause(s, 0, 0); in mac_icr_read()
1044 s->mac_reg[index] = 0; in mac_read_clr4()
1053 s->mac_reg[index] = 0; in mac_read_clr8()
1054 s->mac_reg[index-1] = 0; in mac_read_clr8()
1066 macaddr[0] = cpu_to_le32(s->mac_reg[RA]); in mac_writereg()
1075 s->mac_reg[index] = val & 0xffff; in set_rdt()
1096 s->mac_reg[index] = val & 0xfff80; in set_dlen()
1103 s->mac_reg[TDT] &= 0xffff; in set_tctl()
1111 set_interrupt_cause(s, 0, s->mac_reg[ICR] & ~val); in set_icr()
1118 set_ics(s, 0, 0); in set_imc()
1125 set_ics(s, 0, 0); in set_ims()
1217 static const uint8_t mac_reg_access[0x8000] = {
1265 unsigned int index = (addr & 0x1ffff) >> 2; in e1000_mmio_write()
1271 DBGOUT(GENERAL, "Writing to register at offset: 0x%08x. " in e1000_mmio_write()
1276 DBGOUT(MMIO, "MMIO write attempt to disabled reg. addr=0x%08x\n", in e1000_mmio_write()
1280 DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04"PRIx64"\n", in e1000_mmio_write()
1283 DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08"PRIx64"\n", in e1000_mmio_write()
1292 unsigned int index = (addr & 0x1ffff) >> 2; in e1000_mmio_read()
1298 DBGOUT(GENERAL, "Reading register at offset: 0x%08x. " in e1000_mmio_read()
1303 DBGOUT(MMIO, "MMIO read attempt of disabled reg. addr=0x%08x\n", in e1000_mmio_read()
1307 DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2); in e1000_mmio_read()
1309 return 0; in e1000_mmio_read()
1328 return 0; in e1000_io_read()
1378 return 0; in e1000_pre_save()
1386 s->mit_ide = 0; in e1000_post_load()
1393 nc->link_down = (s->mac_reg[STATUS] & E1000_STATUS_LU) == 0; in e1000_post_load()
1409 return 0; in e1000_post_load()
1416 return 0; in e1000_tx_tso_post_load()
1445 VMSTATE_UINT32_ARRAY(mac_reg, E1000State, 0x8000),
1506 VMSTATE_UINT16_ARRAY(phy_reg, E1000State, 0x20),
1563 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0x0000, 0x0000, 0x0000,
1564 0x3000, 0x1000, 0x6403, 0 /*DevId*/, 0x8086, 0 /*DevId*/, 0x8086, 0x3040,
1565 0x0008, 0x2000, 0x7e14, 0x0048, 0x1000, 0x00d8, 0x0000, 0x2700,
1566 0x6cc9, 0x3150, 0x0722, 0x040b, 0x0984, 0x0000, 0xc000, 0x0706,
1567 0x1008, 0x0000, 0x0f04, 0x7fff, 0x4d01, 0xffff, 0xffff, 0xffff,
1568 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
1569 0x0100, 0x4000, 0x121c, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
1570 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0000,
1586 memory_region_add_coalescing(&d->mmio, 0, excluded_regs[0]); in e1000_mmio_setup()
1587 for (i = 0; excluded_regs[i] != PNPMMIO_SIZE; i++) in e1000_mmio_setup()
1637 /* TODO: RST# value should be 0, PCI spec 6.2.4 */ in pci_e1000_realize()
1638 pci_conf[PCI_CACHE_LINE_SIZE] = 0x10; in pci_e1000_realize()
1644 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio); in pci_e1000_realize()
1711 "bootindex", "/ethernet-phy@0", in e1000_instance_init()
1732 .revision = 0x03,
1738 .revision = 0x03,
1744 .revision = 0x03,
1754 for (i = 0; i < ARRAY_SIZE(e1000_devices); i++) { in e1000_register_types()