87 #define E1000E_MMIO_IDX     0
97 #define E1000E_MSIX_TABLE   (0x0000)
98 #define E1000E_MSIX_PBA     (0x2000)
118     if (s->ioaddr < 0x1FFFF) {  in e1000e_io_get_reg_index()
123     if (s->ioaddr < 0x7FFFF) {  in e1000e_io_get_reg_index()
128     if (s->ioaddr < 0xFFFFF) {  in e1000e_io_get_reg_index()
141     uint32_t idx = 0;  in e1000e_io_read()
154         return 0;  in e1000e_io_read()
157         return 0;  in e1000e_io_read()
166     uint32_t idx = 0;  in e1000e_io_write()
248     0x0000, 0x0000, 0x0000, 0x0420, 0xf746, 0x2010, 0xffff, 0xffff,
250     0x0000, 0x0000, 0x026b, 0x0000, 0x8086, 0x0000, 0x0000, 0x8058,
252     0x0000, 0x2001, 0x7e7c, 0xffff, 0x1000, 0x00c8, 0x0000, 0x2704,
254     0x6cc9, 0x3150, 0x070e, 0x460b, 0x2d84, 0x0100, 0xf000, 0x0706,
256     0x6000, 0x0080, 0x0f04, 0x7fff, 0x4f01, 0xc600, 0x0000, 0x20ff,
258     0x0028, 0x0003, 0x0000, 0x0000, 0x0000, 0x0003, 0x0000, 0xffff,
260     0x0100, 0xc000, 0x121c, 0xc007, 0xffff, 0xffff, 0xffff, 0xffff,
262     0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0x0120, 0xffff, 0x0000,
275     for (i = 0; i < num_vectors; i++) {  in e1000e_unuse_msix_vectors()
284     for (i = 0; i < num_vectors; i++) {  in e1000e_use_msix_vectors()
297                         0xA0, NULL);  in e1000e_init_msix()
299     if (res < 0) {  in e1000e_init_msix()
325     s->core.max_queue_num = s->conf.peers.queues ? s->conf.peers.queues - 1 : 0;  in e1000e_init_net_peer()
341     for (i = 0; i < s->conf.peers.queues; i++) {  in e1000e_init_net_peer()
352     for (i = 0; i < s->conf.peers.queues; i++) {  in e1000e_init_net_peer()
364            (uint64_t)(0x00FF)  << 24 |  in e1000e_gen_dsn()
365            (uint64_t)(0x00FF)  << 32 |  in e1000e_gen_dsn()
368            (uint64_t)(mac[0])  << 56;  in e1000e_gen_dsn()
412     static const uint16_t e1000e_pmrb_offset = 0x0C8;  in e1000e_pci_realize()
413     static const uint16_t e1000e_pcie_offset = 0x0E0;  in e1000e_pci_realize()
414     static const uint16_t e1000e_aer_offset =  0x100;  in e1000e_pci_realize()
415     static const uint16_t e1000e_dsn_offset =  0x140;  in e1000e_pci_realize()
424     pci_dev->config[PCI_CACHE_LINE_SIZE] = 0x10;  in e1000e_pci_realize()
464     if (pcie_endpoint_cap_v1_init(pci_dev, e1000e_pcie_offset) < 0) {  in e1000e_pci_realize()
468     ret = msi_init(PCI_DEVICE(s), 0xD0, 1, true, false, NULL);  in e1000e_pci_realize()
474                                   PCI_PM_CAP_DSI) < 0) {  in e1000e_pci_realize()
479                       PCI_ERR_SIZEOF, NULL) < 0) {  in e1000e_pci_realize()
535     return 0;  in e1000e_pre_save()
597     VMSTATE_STRUCT(_f, _s, 0,                                       \
601     VMSTATE_STRUCT_ARRAY(_f, _s, _num, 0,                           \
650         VMSTATE_STRUCT_ARRAY(core.tx, E1000EState, E1000E_NUM_QUEUES, 0,
670     DEFINE_PROP_SIGNED("subsys", E1000EState, subsys, 0,
686     c->revision = 0;  in e1000e_class_init()
714                                   "bootindex", "/ethernet-phy@0",  in e1000e_instance_init()